Simulation Results: rom_ctrl/64kb

 
20/05/2026 15:30:25 DVSim: v1.38.1 sha: 9c9e49f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.40 %
  • code
  • 90.67 %
  • assert
  • 97.52 %
  • func
  • 92.00 %
  • block
  • 94.28 %
  • line
  • 94.66 %
  • branch
  • 90.59 %
  • toggle
  • 86.94 %
  • FSM
  • 90.48 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 6.000s 401.800us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 6.000s 962.342us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 7.000s 1065.271us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 5.000s 290.298us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 6.000s 555.141us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 6.000s 1707.237us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 7.000s 1065.271us 1 1 100.00
rom_ctrl_csr_aliasing 6.000s 555.141us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 4.000s 1214.913us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 5.000s 1160.064us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 5.000s 435.224us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 18.000s 4037.629us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 10.000s 390.716us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 6.000s 212.316us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 7.000s 1029.145us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 7.000s 1029.145us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 6.000s 962.342us 1 1 100.00
rom_ctrl_csr_rw 7.000s 1065.271us 1 1 100.00
rom_ctrl_csr_aliasing 6.000s 555.141us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.000s 564.109us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 6.000s 962.342us 1 1 100.00
rom_ctrl_csr_rw 7.000s 1065.271us 1 1 100.00
rom_ctrl_csr_aliasing 6.000s 555.141us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.000s 564.109us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 51.000s 2908.677us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 18.000s 20385.766us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 190.000s 2175.085us 1 1 100.00
rom_ctrl_tl_intg_err 42.000s 1299.765us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 190.000s 2175.085us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 190.000s 2175.085us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 51.000s 2908.677us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 51.000s 2908.677us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 51.000s 2908.677us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 51.000s 2908.677us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 51.000s 2908.677us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 190.000s 2175.085us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 190.000s 2175.085us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 6.000s 401.800us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 6.000s 401.800us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 6.000s 401.800us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 42.000s 1299.765us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 51.000s 2908.677us 1 1 100.00
rom_ctrl_kmac_err_chk 10.000s 390.716us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 51.000s 2908.677us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 51.000s 2908.677us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 51.000s 2908.677us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 18.000s 20385.766us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 190.000s 2175.085us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
rom_ctrl_stress_all_with_rand_reset 6.000s 341.510us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:354) scoreboard [scoreboard] alert fatal did not trigger max_delay:* 1 test run
rom_ctrl_stress_all_with_rand_reset 97641113402035446176840724688430474220647831536856036920199047972021657968938 90
UVM_INFO @ 341510445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---