Simulation Results: rstmgr

 
20/05/2026 15:30:25 DVSim: v1.38.1 sha: 9c9e49f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.99 %
  • code
  • 99.13 %
  • assert
  • 98.17 %
  • func
  • 93.67 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 98.18 %
  • toggle
  • 99.43 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.300s 68.025us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.930s 63.675us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.810s 35.850us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 2.550s 114.297us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.420s 44.581us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.440s 66.593us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.810s 35.850us 1 1 100.00
rstmgr_csr_aliasing 1.420s 44.581us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.180s 127.307us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 0.980s 45.796us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.280s 83.271us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 4.350s 527.890us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 4.350s 527.890us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 4.350s 527.890us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 4.350s 527.890us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 1.290s 109.729us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 1.110s 39.058us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.330s 39.351us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.330s 39.351us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.930s 63.675us 1 1 100.00
rstmgr_csr_rw 0.810s 35.850us 1 1 100.00
rstmgr_csr_aliasing 1.420s 44.581us 1 1 100.00
rstmgr_same_csr_outstanding 1.330s 73.894us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.930s 63.675us 1 1 100.00
rstmgr_csr_rw 0.810s 35.850us 1 1 100.00
rstmgr_csr_aliasing 1.420s 44.581us 1 1 100.00
rstmgr_same_csr_outstanding 1.330s 73.894us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 29.760s 6741.874us 1 1 100.00
rstmgr_tl_intg_err 2.630s 386.237us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 29.760s 6741.874us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 29.760s 6741.874us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.630s 386.237us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.000s 60.415us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 3.780s 471.374us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 2.150s 293.399us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 29.760s 6741.874us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.810s 35.850us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.810s 35.850us 1 1 100.00