Simulation Results

Simulation Results: rv_dm/use_dmi_interface

20/05/2026 15:30:25 DVSim: v1.38.1 sha: 9c9e49f json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
86.77 %

code
75.02 %

assert
95.50 %

func
89.80 %

block
89.86 %

line
89.78 %

branch
72.48 %

toggle
75.32 %

FSM
62.50 %

Validation stages

V1		96.30%
V2		69.57%
V2S		100.00%
V3		0.00%
unmapped		0.00%

26/27 passed

96.30 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	rv_dm_smoke	33.000s	2187.597us	1	1	100.00
jtag_dtm_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dtm_csr_hw_reset	31.000s	293.691us	1	1	100.00
jtag_dtm_csr_rw				1	1	100.00
	rv_dm_jtag_dtm_csr_rw	31.000s	611.359us	1	1	100.00
jtag_dtm_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dtm_csr_bit_bash	48.000s	24415.499us	1	1	100.00
jtag_dtm_csr_aliasing				1	1	100.00
	rv_dm_jtag_dtm_csr_aliasing	30.000s	262.861us	1	1	100.00
jtag_dmi_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dmi_csr_hw_reset	37.000s	11266.301us	1	1	100.00
jtag_dmi_csr_rw				1	1	100.00
	rv_dm_jtag_dmi_csr_rw	35.000s	2860.320us	1	1	100.00
jtag_dmi_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dmi_csr_bit_bash	41.000s	9474.917us	1	1	100.00
jtag_dmi_csr_aliasing				1	1	100.00
	rv_dm_jtag_dmi_csr_aliasing	64.000s	212172.728us	1	1	100.00
jtag_dmi_cmderr_busy				1	1	100.00
	rv_dm_cmderr_busy	32.000s	661.408us	1	1	100.00
jtag_dmi_cmderr_not_supported				1	1	100.00
	rv_dm_cmderr_not_supported	30.000s	333.226us	1	1	100.00
cmderr_exception				1	1	100.00
	rv_dm_cmderr_exception	31.000s	377.025us	1	1	100.00
mem_tl_access_resuming				0	1	0.00
	rv_dm_mem_tl_access_resuming	30.000s	136.318us	0	1	0.00
mem_tl_access_halted				1	1	100.00
	rv_dm_mem_tl_access_halted	30.000s	367.876us	1	1	100.00
cmderr_halt_resume				1	1	100.00
	rv_dm_cmderr_halt_resume	32.000s	745.648us	1	1	100.00
dataaddr_rw_access				1	1	100.00
	rv_dm_dataaddr_rw_access	32.000s	165.516us	1	1	100.00
halt_resume				1	1	100.00
	rv_dm_halt_resume_whereto	31.000s	826.575us	1	1	100.00
progbuf_busy				1	1	100.00
	rv_dm_cmderr_busy	32.000s	661.408us	1	1	100.00
abstractcmd_status				1	1	100.00
	rv_dm_abstractcmd_status	30.000s	770.811us	1	1	100.00
progbuf_read_write_execute				1	1	100.00
	rv_dm_progbuf_read_write_execute	31.000s	286.595us	1	1	100.00
progbuf_exception				1	1	100.00
	rv_dm_cmderr_exception	31.000s	377.025us	1	1	100.00
rom_read_access				1	1	100.00
	rv_dm_rom_read_access	30.000s	77.625us	1	1	100.00
csr_hw_reset				1	1	100.00
	rv_dm_csr_hw_reset	36.000s	365.909us	1	1	100.00
csr_rw				1	1	100.00
	rv_dm_csr_rw	36.000s	787.996us	1	1	100.00
csr_bit_bash				1	1	100.00
	rv_dm_csr_bit_bash	57.000s	20085.785us	1	1	100.00
csr_aliasing				1	1	100.00
	rv_dm_csr_aliasing	61.000s	16123.674us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	rv_dm_csr_mem_rw_with_rand_reset	32.000s	722.186us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	rv_dm_csr_aliasing	61.000s	16123.674us	1	1	100.00
	rv_dm_csr_rw	36.000s	787.996us	1	1	100.00
mem_walk				1	1	100.00
	rv_dm_mem_walk	30.000s	65.207us	1	1	100.00
mem_partial_access				1	1	100.00
	rv_dm_mem_partial_access	36.000s	159.114us	1	1	100.00

16/23 passed

69.57 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				1	1	100.00
	rv_dm_smoke	33.000s	2187.597us	1	1	100.00
jtag_dtm_hard_reset				1	1	100.00
	rv_dm_jtag_dtm_hard_reset	31.000s	663.850us	1	1	100.00
jtag_dtm_idle_hint				1	1	100.00
	rv_dm_jtag_dtm_idle_hint	31.000s	149.294us	1	1	100.00
jtag_dmi_failed_op				1	1	100.00
	rv_dm_dmi_failed_op	31.000s	192.038us	1	1	100.00
jtag_dmi_dm_inactive				1	1	100.00
	rv_dm_jtag_dmi_dm_inactive	33.000s	728.160us	1	1	100.00
sba				0	2	0.00
	rv_dm_sba_tl_access	32.000s	839.999us	0	1	0.00
	rv_dm_delayed_resp_sba_tl_access	31.000s	67.668us	0	1	0.00
bad_sba				0	1	0.00
	rv_dm_bad_sba_tl_access	32.000s	2755.876us	0	1	0.00
sba_autoincrement				0	1	0.00
	rv_dm_autoincr_sba_tl_access	86.000s	32550.230us	0	1	0.00
jtag_dmi_debug_disabled				0	1	0.00
	rv_dm_jtag_dmi_debug_disabled	31.000s	226.911us	0	1	0.00
sba_debug_disabled				1	1	100.00
	rv_dm_sba_debug_disabled	30.000s	1190.987us	1	1	100.00
ndmreset_req				1	1	100.00
	rv_dm_ndmreset_req	33.000s	185.471us	1	1	100.00
hart_unavail				0	1	0.00
	rv_dm_hart_unavail	31.000s	226.534us	0	1	0.00
tap_ctrl_transitions				2	2	100.00
	rv_dm_tap_fsm	35.000s	6720.754us	1	1	100.00
	rv_dm_tap_fsm_rand_reset	50.000s	4220.643us	1	1	100.00
hartsel_warl				1	1	100.00
	rv_dm_hartsel_warl	30.000s	309.015us	1	1	100.00
stress_all				0	1	0.00
	rv_dm_stress_all	9138.000s	10000000.000us	0	1	0.00
alert_test				1	1	100.00
	rv_dm_alert_test	30.000s	225.327us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	rv_dm_tl_errors	33.000s	4803.602us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	rv_dm_tl_errors	33.000s	4803.602us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	rv_dm_csr_aliasing	61.000s	16123.674us	1	1	100.00
	rv_dm_csr_hw_reset	36.000s	365.909us	1	1	100.00
	rv_dm_csr_rw	36.000s	787.996us	1	1	100.00
	rv_dm_same_csr_outstanding	36.000s	467.671us	1	1	100.00
tl_d_partial_access				4	4	100.00
	rv_dm_csr_aliasing	61.000s	16123.674us	1	1	100.00
	rv_dm_csr_hw_reset	36.000s	365.909us	1	1	100.00
	rv_dm_csr_rw	36.000s	787.996us	1	1	100.00
	rv_dm_same_csr_outstanding	36.000s	467.671us	1	1	100.00

V2S

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	rv_dm_sec_cm	31.000s	1413.080us	1	1	100.00
	rv_dm_tl_intg_err	34.000s	1161.383us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	rv_dm_tl_intg_err	34.000s	1161.383us	1	1	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	30.000s	1190.987us	1	1	100.00
	rv_dm_debug_disabled	34.000s	178.190us	1	1	100.00
sec_cm_lc_dft_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	30.000s	1190.987us	1	1	100.00
	rv_dm_debug_disabled	34.000s	178.190us	1	1	100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				1	1	100.00
	rv_dm_smoke	33.000s	2187.597us	1	1	100.00
sec_cm_dm_en_ctrl_lc_gated				1	1	100.00
	rv_dm_buffered_enable	31.000s	141.105us	1	1	100.00
sec_cm_sba_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	31.000s	92.904us	1	1	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	31.000s	92.904us	1	1	100.00
sec_cm_exec_ctrl_mubi				1	1	100.00
	rv_dm_buffered_enable	31.000s	141.105us	1	1	100.00

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	1	0.00
	rv_dm_stress_all_with_rand_reset	37.000s	712.218us	0	1	0.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	519.000s	300000.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (rv_dm_scoreboard.sv:414) [scoreboard] sba_tl_access_q item uncompared:				3 test runs
	rv_dm_sba_tl_access	85034718961486274283206970838731602986491454081876912848543375944114515154371	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24217
	rv_dm_bad_sba_tl_access	36572008045196575788810060295277237051022728564554959624991329448265569943786	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24201
	rv_dm_autoincr_sba_tl_access	24615470321682816392707748292361918753658979307530177012764713202204747793139	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24243
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == 'b (* [] vs [*])				2 test runs
	rv_dm_mem_tl_access_resuming	7060343196469390806290678232545885493782826177594098555790900739999505207290	87	UVM_INFO @ 136317563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	46762147421192742705850999963184923648255735987095913628030865874425366365678	105	UVM_INFO @ 712217920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				2 test runs
	rv_dm_scanmode	84934546393010241620138023251946571056143902364204065940871163243724336341841	87	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	104535666256332226054371646923255529362413405353610728698634840162022392130986	89	UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (tl_device_seq.sv:151) sequencer [m_tl_sba_device_seq] Cannot randomize rsp				1 test run
	rv_dm_delayed_resp_sba_tl_access	27595412235853921469007126067030350326505923336440638535043420995125185154299	107	UVM_INFO @ 67668430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [] vs [*])				1 test run
	rv_dm_hart_unavail	59620008714703994949514606360402539172779590382101885602445193638232906179781	87	UVM_INFO @ 226534491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [] vs [*])				1 test run
	rv_dm_jtag_dmi_debug_disabled	86919050929959870805737947767136735708938384977004233067432202298086000562306	87	UVM_INFO @ 226911294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---