Simulation Results: rv_timer

 
20/05/2026 15:30:25 DVSim: v1.38.1 sha: 9c9e49f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.84 %
  • code
  • 95.85 %
  • assert
  • 98.10 %
  • func
  • 99.58 %
  • block
  • 99.10 %
  • line
  • 99.02 %
  • branch
  • 99.26 %
  • toggle
  • 89.26 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 2.000s 159.177us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 1.000s 29.159us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 1.000s 47.287us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.000s 272.916us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 1.000s 311.159us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 1.000s 21.960us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 1.000s 47.287us 1 1 100.00
rv_timer_csr_aliasing 1.000s 311.159us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 1.000s 522.597us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 4.000s 2216.951us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 71.000s 204397.122us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 71.000s 204397.122us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 3.000s 2143.588us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 1.000s 38.208us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 1.000s 32.967us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 2.000s 471.570us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 2.000s 471.570us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 29.159us 1 1 100.00
rv_timer_csr_rw 1.000s 47.287us 1 1 100.00
rv_timer_csr_aliasing 1.000s 311.159us 1 1 100.00
rv_timer_same_csr_outstanding 1.000s 18.191us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 29.159us 1 1 100.00
rv_timer_csr_rw 1.000s 47.287us 1 1 100.00
rv_timer_csr_aliasing 1.000s 311.159us 1 1 100.00
rv_timer_same_csr_outstanding 1.000s 18.191us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 1.000s 313.271us 1 1 100.00
rv_timer_tl_intg_err 2.000s 114.226us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 2.000s 114.226us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 4.000s 705.549us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 1.000s 49.156us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 36.000s 29912.117us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:165) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 2 test runs
rv_timer_min 32275014259367266517383423640170516000884501436558801471462601453899097571772 85
UVM_INFO @ 705549309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 39812682963154171727191927772240037439184505329753330464614188944339814009799 85
UVM_INFO @ 522597373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 66958167421251421945975421196452971722435982162125821359810759511623100713069 84
UVM_INFO @ 49155740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---