Simulation Results: spi_device/1r1w

 
20/05/2026 15:30:25 DVSim: v1.38.1 sha: 9c9e49f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.90 %
  • code
  • 91.52 %
  • assert
  • 95.39 %
  • func
  • 64.79 %
  • block
  • 98.26 %
  • line
  • 98.57 %
  • branch
  • 96.83 %
  • toggle
  • 81.09 %
  • FSM
  • 89.58 %
Validation stages
V1
100.00%
V2
92.31%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 224.000s 138085.152us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 2.000s 74.969us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 2.000s 38.594us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 40.000s 2765.121us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 14.000s 4270.334us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 3.000s 396.046us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 2.000s 38.594us 1 1 100.00
spi_device_csr_aliasing 14.000s 4270.334us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 2.000s 20.153us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 3.000s 27.589us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 2.000s 20.573us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 2.000s 20.802us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 1.000s 12.730us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 3.000s 85.803us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 3.000s 85.803us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 8.000s 909.414us 1 1 100.00
spi_device_tpm_sts_read 2.000s 962.409us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 27.000s 3953.432us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 4.000s 460.620us 1 1 100.00
spi_device_flash_all 36.000s 7094.122us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 26.000s 14627.237us 1 1 100.00
spi_device_flash_all 36.000s 7094.122us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 26.000s 14627.237us 1 1 100.00
spi_device_flash_all 36.000s 7094.122us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 36.000s 7094.122us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 5.000s 246.227us 1 1 100.00
spi_device_flash_all 36.000s 7094.122us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 5.000s 246.227us 1 1 100.00
spi_device_flash_all 36.000s 7094.122us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 5.000s 246.227us 1 1 100.00
spi_device_flash_all 36.000s 7094.122us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 5.000s 246.227us 1 1 100.00
spi_device_flash_all 36.000s 7094.122us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 5.000s 246.227us 1 1 100.00
spi_device_flash_all 36.000s 7094.122us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 4.000s 108.842us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 3.000s 195.936us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 3.000s 195.936us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 3.000s 195.936us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 6.000s 254.702us 1 1 100.00
spi_device_read_buffer_direct 10.000s 544.187us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 3.000s 195.936us 1 1 100.00
spi_device_flash_all 36.000s 7094.122us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 36.000s 7094.122us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 36.000s 7094.122us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 9.000s 658.608us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 9.000s 658.608us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 224.000s 138085.152us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 106.000s 18682.182us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 85.000s 13673.244us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 1.000s 11.618us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 2.000s 16.166us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 2.000s 197.123us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 2.000s 197.123us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 2.000s 74.969us 1 1 100.00
spi_device_csr_rw 2.000s 38.594us 1 1 100.00
spi_device_csr_aliasing 14.000s 4270.334us 1 1 100.00
spi_device_same_csr_outstanding 5.000s 145.632us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 2.000s 74.969us 1 1 100.00
spi_device_csr_rw 2.000s 38.594us 1 1 100.00
spi_device_csr_aliasing 14.000s 4270.334us 1 1 100.00
spi_device_same_csr_outstanding 5.000s 145.632us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 2.000s 258.820us 1 1 100.00
spi_device_tl_intg_err 12.000s 808.456us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 12.000s 808.456us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 2.000s 26.010us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ1] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice) 1 test run
spi_device_mem_parity 93323330427072670919744460029273121837050102243410008772943140484309989986796 87
UVM_ERROR @ 17801921 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
ERROR: VHPI NOTFOUND
Name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[993] not found within the scope .
UVM_ERROR @ 17801921 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ2] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[993] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 98595971325363220066552241510900942299372838753161691489643286858666479475144 85
UVM_ERROR @ 9935421 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x638afc [11000111000101011111100] vs 0x0 [0])
UVM_ERROR @ 9984421 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x42ac34 [10000101010110000110100] vs 0x0 [0])
UVM_ERROR @ 10051421 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xc53f42 [110001010011111101000010] vs 0x0 [0])
UVM_ERROR @ 10120421 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xbb82b [10111011100000101011] vs 0x0 [0])