Simulation Results: sram_ctrl/main

 
20/05/2026 15:30:25 DVSim: v1.38.1 sha: 9c9e49f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.45 %
  • code
  • 96.06 %
  • assert
  • 97.68 %
  • func
  • 92.60 %
  • block
  • 95.14 %
  • line
  • 95.77 %
  • branch
  • 92.38 %
  • toggle
  • 96.09 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 1013.990us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 24.048us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 14.995us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 586.232us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 18.394us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 365.539us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 14.995us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 18.394us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 220.000s 21212.118us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 69.000s 9640.646us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 9.000s 3920.218us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 138.000s 4607.050us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 108.000s 6036.266us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 19.000s 8938.286us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 21.000s 5807.961us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 24.000s 5367.749us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 4.000s 376.390us 1 1 100.00
sram_ctrl_partial_access_b2b 226.000s 36242.219us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 4.000s 2689.003us 1 1 100.00
sram_ctrl_throughput_w_partial_write 5.000s 742.406us 1 1 100.00
sram_ctrl_throughput_w_readback 5.000s 2685.692us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 12.000s 14158.053us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 4.000s 1411.489us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 270.000s 49983.189us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 12.210us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 263.327us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 263.327us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 24.048us 1 1 100.00
sram_ctrl_csr_rw 1.000s 14.995us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 18.394us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 15.304us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 24.048us 1 1 100.00
sram_ctrl_csr_rw 1.000s 14.995us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 18.394us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 15.304us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 13.000s 7513.531us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 209.892us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 302.525us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 209.892us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 302.525us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 12.000s 14158.053us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 12.000s 14158.053us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 14.995us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 24.000s 5367.749us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 24.000s 5367.749us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 24.000s 5367.749us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 21.000s 5807.961us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 3.000s 1422.258us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 13.000s 7513.531us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 4.000s 674.017us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 1013.990us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 1013.990us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 24.000s 5367.749us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 209.892us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 21.000s 5807.961us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 209.892us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 209.892us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 1013.990us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 209.892us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 19.000s 9661.814us 1 1 100.00