Simulation Results: uart

 
20/05/2026 15:30:25 DVSim: v1.38.1 sha: 9c9e49f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.75 %
  • code
  • 96.44 %
  • assert
  • 97.12 %
  • func
  • 90.69 %
  • block
  • 98.83 %
  • line
  • 99.24 %
  • branch
  • 97.79 %
  • toggle
  • 88.74 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 2.000s 521.954us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 2.000s 58.779us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 1.000s 187.481us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 2.000s 249.334us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 2.000s 113.042us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 1.000s 115.595us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 1.000s 187.481us 1 1 100.00
uart_csr_aliasing 2.000s 113.042us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 8.000s 9005.699us 1 1 100.00
parity 2 2 100.00
uart_smoke 2.000s 521.954us 1 1 100.00
uart_tx_rx 8.000s 9005.699us 1 1 100.00
parity_error 2 2 100.00
uart_intr 353.000s 300876.399us 1 1 100.00
uart_rx_parity_err 44.000s 126653.781us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 8.000s 9005.699us 1 1 100.00
uart_intr 353.000s 300876.399us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 156.000s 126510.449us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 43.000s 123510.389us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 55.000s 78062.174us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 353.000s 300876.399us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 353.000s 300876.399us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 353.000s 300876.399us 1 1 100.00
perf 1 1 100.00
uart_perf 24.000s 3326.425us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 5.000s 5068.485us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 5.000s 5068.485us 1 1 100.00
rx_noise_filter 1 1 100.00
uart_noise_filter 17.000s 38672.622us 1 1 100.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 16.000s 33910.627us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 4.000s 1415.994us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 11.000s 5591.760us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 271.000s 115579.342us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 87.000s 246985.403us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 1.000s 18.579us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 1.000s 44.155us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 2.000s 388.247us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 2.000s 388.247us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 2.000s 58.779us 1 1 100.00
uart_csr_rw 1.000s 187.481us 1 1 100.00
uart_csr_aliasing 2.000s 113.042us 1 1 100.00
uart_same_csr_outstanding 2.000s 84.703us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 2.000s 58.779us 1 1 100.00
uart_csr_rw 1.000s 187.481us 1 1 100.00
uart_csr_aliasing 2.000s 113.042us 1 1 100.00
uart_same_csr_outstanding 2.000s 84.703us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 1.000s 62.624us 1 1 100.00
uart_tl_intg_err 1.000s 577.143us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.000s 577.143us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
uart_stress_all_with_rand_reset 10.000s 13781.275us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:465) [uart_common_vseq] wait timeout occurred! 1 test run
uart_stress_all_with_rand_reset 51647998018881634532139657450727904582649557203318204313186777152501799497864 114
UVM_INFO @ 13781274931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---