Simulation Results: ac_range_check

 
22/05/2026 03:08:15 DVSim: v1.49.0 sha: d71121d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.01 %
  • code
  • 93.21 %
  • assert
  • 97.75 %
  • func
  • 58.07 %
  • block
  • 99.10 %
  • line
  • 99.93 %
  • branch
  • 98.24 %
  • toggle
  • 81.45 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 1 1 100.00
ac_range_check_smoke 23.000s 1759.498us 1 1 100.00
ac_range_check_smoke_racl 1 1 100.00
ac_range_check_smoke_racl 47.000s 2386.481us 1 1 100.00
csr_hw_reset 1 1 100.00
ac_range_check_csr_hw_reset 2.000s 75.447us 1 1 100.00
csr_rw 1 1 100.00
ac_range_check_csr_rw 3.000s 696.963us 1 1 100.00
csr_bit_bash 1 1 100.00
ac_range_check_csr_bit_bash 37.000s 11769.766us 1 1 100.00
csr_aliasing 1 1 100.00
ac_range_check_csr_aliasing 13.000s 363.092us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
ac_range_check_csr_mem_rw_with_rand_reset 2.000s 191.954us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
ac_range_check_csr_rw 3.000s 696.963us 1 1 100.00
ac_range_check_csr_aliasing 13.000s 363.092us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 1 1 100.00
ac_range_check_lock_range 3.000s 305.202us 1 1 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 29.000s 2730.147us 1 1 100.00
stress_all 1 1 100.00
ac_range_check_stress_all 84.000s 3845.425us 1 1 100.00
alert_test 1 1 100.00
ac_range_check_alert_test 2.000s 18.810us 1 1 100.00
intr_test 1 1 100.00
ac_range_check_intr_test 1.000s 42.880us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
ac_range_check_tl_errors 2.000s 37.921us 1 1 100.00
tl_d_illegal_access 1 1 100.00
ac_range_check_tl_errors 2.000s 37.921us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
ac_range_check_csr_hw_reset 2.000s 75.447us 1 1 100.00
ac_range_check_csr_rw 3.000s 696.963us 1 1 100.00
ac_range_check_csr_aliasing 13.000s 363.092us 1 1 100.00
ac_range_check_same_csr_outstanding 3.000s 138.339us 1 1 100.00
tl_d_partial_access 4 4 100.00
ac_range_check_csr_hw_reset 2.000s 75.447us 1 1 100.00
ac_range_check_csr_rw 3.000s 696.963us 1 1 100.00
ac_range_check_csr_aliasing 13.000s 363.092us 1 1 100.00
ac_range_check_same_csr_outstanding 3.000s 138.339us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
ac_range_check_shadow_reg_errors 10.000s 1590.206us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
ac_range_check_shadow_reg_errors 10.000s 1590.206us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
ac_range_check_shadow_reg_errors 10.000s 1590.206us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
ac_range_check_shadow_reg_errors 10.000s 1590.206us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 55.000s 1401.686us 1 1 100.00
tl_intg_err 2 2 100.00
ac_range_check_sec_cm 2.000s 13.447us 1 1 100.00
ac_range_check_tl_intg_err 8.000s 682.616us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
ac_range_check_stress_all_with_rand_reset 266.000s 1521.294us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
ac_range_check_smoke_high_threshold 23.000s 1708.031us 1 1 100.00