Simulation Results: aes/gcm_masked

 
22/05/2026 03:08:15 DVSim: v1.49.0 sha: d71121d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.97 %
  • code
  • 95.70 %
  • assert
  • 98.29 %
  • func
  • 69.91 %
  • block
  • 95.89 %
  • line
  • 97.55 %
  • branch
  • 89.80 %
  • toggle
  • 98.05 %
  • FSM
  • 97.42 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 83.338us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 440.041us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 57.778us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 65.517us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 6.000s 190.729us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 336.627us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 119.170us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 65.517us 1 1 100.00
aes_csr_aliasing 2.000s 336.627us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 440.041us 1 1 100.00
aes_config_error 5.000s 87.216us 1 1 100.00
aes_stress 5.000s 226.391us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 440.041us 1 1 100.00
aes_config_error 5.000s 87.216us 1 1 100.00
aes_stress 5.000s 226.391us 1 1 100.00
back2back 2 2 100.00
aes_stress 5.000s 226.391us 1 1 100.00
aes_b2b 15.000s 718.196us 1 1 100.00
backpressure 1 1 100.00
aes_stress 5.000s 226.391us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 3.000s 440.041us 1 1 100.00
aes_config_error 5.000s 87.216us 1 1 100.00
aes_stress 5.000s 226.391us 1 1 100.00
aes_alert_reset 4.000s 238.116us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 104.782us 1 1 100.00
aes_config_error 5.000s 87.216us 1 1 100.00
aes_alert_reset 4.000s 238.116us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 4.000s 404.443us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 7.000s 212.702us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 8.000s 382.716us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 4.000s 238.116us 1 1 100.00
stress 1 1 100.00
aes_stress 5.000s 226.391us 1 1 100.00
sideload 2 2 100.00
aes_stress 5.000s 226.391us 1 1 100.00
aes_sideload 9.000s 566.082us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 200.602us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 41.000s 4140.204us 1 1 100.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 3.000s 92.737us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 109.205us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 194.042us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 194.042us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 57.778us 1 1 100.00
aes_csr_rw 2.000s 65.517us 1 1 100.00
aes_csr_aliasing 2.000s 336.627us 1 1 100.00
aes_same_csr_outstanding 2.000s 69.111us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 57.778us 1 1 100.00
aes_csr_rw 2.000s 65.517us 1 1 100.00
aes_csr_aliasing 2.000s 336.627us 1 1 100.00
aes_same_csr_outstanding 2.000s 69.111us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 3.000s 99.201us 1 1 100.00
fault_inject 3 3 100.00
aes_fi 3.000s 362.105us 1 1 100.00
aes_control_fi 3.000s 95.352us 1 1 100.00
aes_cipher_fi 2.000s 45.619us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 1.000s 259.773us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 1.000s 259.773us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 1.000s 259.773us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 1.000s 259.773us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 849.674us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 5.000s 947.754us 1 1 100.00
aes_tl_intg_err 3.000s 924.171us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 924.171us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 4.000s 238.116us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 259.773us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 259.773us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 3.000s 440.041us 1 1 100.00
aes_stress 5.000s 226.391us 1 1 100.00
aes_alert_reset 4.000s 238.116us 1 1 100.00
aes_core_fi 2.000s 68.766us 1 1 100.00
sec_cm_gcm_config_sparse 4 4 100.00
aes_gcm_save_restore 3.000s 92.737us 1 1 100.00
aes_config_error 5.000s 87.216us 1 1 100.00
aes_stress 5.000s 226.391us 1 1 100.00
aes_core_fi 2.000s 68.766us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 259.773us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 3.000s 62.697us 1 1 100.00
aes_stress 5.000s 226.391us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 5.000s 226.391us 1 1 100.00
aes_sideload 9.000s 566.082us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 3.000s 62.697us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 3.000s 62.697us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 3.000s 62.697us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 3.000s 62.697us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 3.000s 62.697us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 5.000s 226.391us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 5.000s 226.391us 1 1 100.00
sec_cm_main_fsm_sparse 1 1 100.00
aes_fi 3.000s 362.105us 1 1 100.00
sec_cm_main_fsm_redun 4 4 100.00
aes_fi 3.000s 362.105us 1 1 100.00
aes_control_fi 3.000s 95.352us 1 1 100.00
aes_cipher_fi 2.000s 45.619us 1 1 100.00
aes_ctr_fi 3.000s 158.602us 1 1 100.00
sec_cm_cipher_fsm_sparse 1 1 100.00
aes_fi 3.000s 362.105us 1 1 100.00
sec_cm_cipher_fsm_redun 3 3 100.00
aes_fi 3.000s 362.105us 1 1 100.00
aes_control_fi 3.000s 95.352us 1 1 100.00
aes_cipher_fi 2.000s 45.619us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 45.619us 1 1 100.00
sec_cm_ctr_fsm_sparse 1 1 100.00
aes_fi 3.000s 362.105us 1 1 100.00
sec_cm_ctr_fsm_redun 3 3 100.00
aes_fi 3.000s 362.105us 1 1 100.00
aes_control_fi 3.000s 95.352us 1 1 100.00
aes_ctr_fi 3.000s 158.602us 1 1 100.00
sec_cm_ghash_fsm_sparse 1 1 100.00
aes_fi 3.000s 362.105us 1 1 100.00
sec_cm_ctrl_sparse 4 4 100.00
aes_fi 3.000s 362.105us 1 1 100.00
aes_control_fi 3.000s 95.352us 1 1 100.00
aes_cipher_fi 2.000s 45.619us 1 1 100.00
aes_ctr_fi 3.000s 158.602us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 4.000s 238.116us 1 1 100.00
sec_cm_main_fsm_local_esc 4 4 100.00
aes_fi 3.000s 362.105us 1 1 100.00
aes_control_fi 3.000s 95.352us 1 1 100.00
aes_cipher_fi 2.000s 45.619us 1 1 100.00
aes_ctr_fi 3.000s 158.602us 1 1 100.00
sec_cm_cipher_fsm_local_esc 4 4 100.00
aes_fi 3.000s 362.105us 1 1 100.00
aes_control_fi 3.000s 95.352us 1 1 100.00
aes_cipher_fi 2.000s 45.619us 1 1 100.00
aes_ctr_fi 3.000s 158.602us 1 1 100.00
sec_cm_ctr_fsm_local_esc 3 3 100.00
aes_fi 3.000s 362.105us 1 1 100.00
aes_control_fi 3.000s 95.352us 1 1 100.00
aes_ctr_fi 3.000s 158.602us 1 1 100.00
sec_cm_ghash_fsm_local_esc 2 2 100.00
aes_ghash_fi 3.000s 114.331us 1 1 100.00
aes_fi 3.000s 362.105us 1 1 100.00
sec_cm_data_reg_local_esc 3 3 100.00
aes_fi 3.000s 362.105us 1 1 100.00
aes_control_fi 3.000s 95.352us 1 1 100.00
aes_cipher_fi 2.000s 45.619us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 97.000s 21483.540us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_base_vseq.sv:307) virtual_sequencer [aes_stress_vseq] Expected GCM phase GCM_AAD, got GCM_TEXT 1 test run
aes_stress_all_with_rand_reset 53120091868902329182077570415273573361095003978262594317056960071485727733290 3477
UVM_INFO @ 21483540031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---