Simulation Results: aes/gcm_unmasked

 
22/05/2026 03:08:15 DVSim: v1.49.0 sha: d71121d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 84.82 %
  • code
  • 91.30 %
  • assert
  • 97.75 %
  • func
  • 65.42 %
  • block
  • 91.05 %
  • line
  • 92.41 %
  • branch
  • 84.02 %
  • toggle
  • 97.99 %
  • FSM
  • 90.78 %
Validation stages
V1
100.00%
V2
100.00%
V2S
93.75%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 84.403us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 97.371us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 186.702us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 86.797us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 5.000s 333.382us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 4.000s 4198.061us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 86.920us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 86.797us 1 1 100.00
aes_csr_aliasing 4.000s 4198.061us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 97.371us 1 1 100.00
aes_config_error 2.000s 102.943us 1 1 100.00
aes_stress 3.000s 263.035us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 97.371us 1 1 100.00
aes_config_error 2.000s 102.943us 1 1 100.00
aes_stress 3.000s 263.035us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 263.035us 1 1 100.00
aes_b2b 5.000s 263.851us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 263.035us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 97.371us 1 1 100.00
aes_config_error 2.000s 102.943us 1 1 100.00
aes_stress 3.000s 263.035us 1 1 100.00
aes_alert_reset 2.000s 70.530us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 66.224us 1 1 100.00
aes_config_error 2.000s 102.943us 1 1 100.00
aes_alert_reset 2.000s 70.530us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 2.000s 134.771us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 3.000s 197.817us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 2.000s 70.530us 1 1 100.00
stress 1 1 100.00
aes_stress 3.000s 263.035us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 263.035us 1 1 100.00
aes_sideload 2.000s 80.815us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 75.965us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 10.000s 1502.159us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 52.694us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 146.323us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 146.323us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 186.702us 1 1 100.00
aes_csr_rw 1.000s 86.797us 1 1 100.00
aes_csr_aliasing 4.000s 4198.061us 1 1 100.00
aes_same_csr_outstanding 2.000s 111.454us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 186.702us 1 1 100.00
aes_csr_rw 1.000s 86.797us 1 1 100.00
aes_csr_aliasing 4.000s 4198.061us 1 1 100.00
aes_same_csr_outstanding 2.000s 111.454us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 3.000s 204.557us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 2.000s 246.448us 1 1 100.00
aes_control_fi 1.000s 47.025us 1 1 100.00
aes_cipher_fi 17.000s 10010.537us 0 1 0.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 287.491us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 287.491us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 287.491us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 287.491us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 204.366us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 2.000s 500.354us 1 1 100.00
aes_tl_intg_err 2.000s 712.743us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 712.743us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 2.000s 70.530us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 287.491us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 287.491us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 2.000s 97.371us 1 1 100.00
aes_stress 3.000s 263.035us 1 1 100.00
aes_alert_reset 2.000s 70.530us 1 1 100.00
aes_core_fi 1.000s 73.801us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 2.000s 102.943us 1 1 100.00
aes_stress 3.000s 263.035us 1 1 100.00
aes_core_fi 1.000s 73.801us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 287.491us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 91.614us 1 1 100.00
aes_stress 3.000s 263.035us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 263.035us 1 1 100.00
aes_sideload 2.000s 80.815us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 91.614us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 91.614us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 91.614us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 91.614us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 91.614us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 263.035us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 263.035us 1 1 100.00
sec_cm_main_fsm_sparse 1 1 100.00
aes_fi 2.000s 246.448us 1 1 100.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 2.000s 246.448us 1 1 100.00
aes_control_fi 1.000s 47.025us 1 1 100.00
aes_cipher_fi 17.000s 10010.537us 0 1 0.00
aes_ctr_fi 2.000s 52.855us 1 1 100.00
sec_cm_cipher_fsm_sparse 1 1 100.00
aes_fi 2.000s 246.448us 1 1 100.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 2.000s 246.448us 1 1 100.00
aes_control_fi 1.000s 47.025us 1 1 100.00
aes_cipher_fi 17.000s 10010.537us 0 1 0.00
sec_cm_cipher_ctr_redun 0 1 0.00
aes_cipher_fi 17.000s 10010.537us 0 1 0.00
sec_cm_ctr_fsm_sparse 1 1 100.00
aes_fi 2.000s 246.448us 1 1 100.00
sec_cm_ctr_fsm_redun 3 3 100.00
aes_fi 2.000s 246.448us 1 1 100.00
aes_control_fi 1.000s 47.025us 1 1 100.00
aes_ctr_fi 2.000s 52.855us 1 1 100.00
sec_cm_ghash_fsm_sparse 1 1 100.00
aes_fi 2.000s 246.448us 1 1 100.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 2.000s 246.448us 1 1 100.00
aes_control_fi 1.000s 47.025us 1 1 100.00
aes_cipher_fi 17.000s 10010.537us 0 1 0.00
aes_ctr_fi 2.000s 52.855us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 2.000s 70.530us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 2.000s 246.448us 1 1 100.00
aes_control_fi 1.000s 47.025us 1 1 100.00
aes_cipher_fi 17.000s 10010.537us 0 1 0.00
aes_ctr_fi 2.000s 52.855us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 2.000s 246.448us 1 1 100.00
aes_control_fi 1.000s 47.025us 1 1 100.00
aes_cipher_fi 17.000s 10010.537us 0 1 0.00
aes_ctr_fi 2.000s 52.855us 1 1 100.00
sec_cm_ctr_fsm_local_esc 3 3 100.00
aes_fi 2.000s 246.448us 1 1 100.00
aes_control_fi 1.000s 47.025us 1 1 100.00
aes_ctr_fi 2.000s 52.855us 1 1 100.00
sec_cm_ghash_fsm_local_esc 1 1 100.00
aes_fi 2.000s 246.448us 1 1 100.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 2.000s 246.448us 1 1 100.00
aes_control_fi 1.000s 47.025us 1 1 100.00
aes_cipher_fi 17.000s 10010.537us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 8.000s 139.090us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! 1 test run
aes_cipher_fi 110690014631234196925819063096913807067739615520015056148672027951911916736131 144
UVM_INFO @ 10010536536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:76) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) 1 test run
aes_stress_all_with_rand_reset 87609186387887802039710686431285443973879421548779269956418375221861855642038 468
UVM_INFO @ 139089806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---