Simulation Results: alert_handler

 
22/05/2026 03:08:15 DVSim: v1.49.0 sha: d71121d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 88.71 %
  • code
  • 89.99 %
  • assert
  • 98.11 %
  • func
  • 78.02 %
  • line
  • 99.72 %
  • branch
  • 97.85 %
  • cond
  • 90.41 %
  • toggle
  • 84.53 %
  • FSM
  • 77.42 %
Validation stages
V1
100.00%
V2
89.47%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 17.430s 303.405us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 2.880s 80.186us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 4.140s 129.842us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 92.370s 3699.577us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 200.190s 45662.199us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 8.050s 63.631us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 4.140s 129.842us 1 1 100.00
alert_handler_csr_aliasing 200.190s 45662.199us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 68.540s 9840.056us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 29.410s 2963.285us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 1105.700s 16142.026us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 8.280s 595.675us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 17.430s 303.405us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 23.390s 1995.356us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 60.260s 5712.679us 1 1 100.00
ping_timeout 0 1 0.00
alert_handler_ping_timeout 41.110s 2182.379us 0 1 0.00
lpg 2 2 100.00
alert_handler_lpg 622.240s 111268.587us 1 1 100.00
alert_handler_lpg_stub_clk 884.970s 20356.369us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 1589.450s 39761.043us 1 1 100.00
alert_handler_entropy_stress_test 0 1 0.00
alert_handler_entropy_stress 11.090s 1049.999us 0 1 0.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 2.170s 24.990us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.400s 15.862us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 13.260s 289.193us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 13.260s 289.193us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 2.880s 80.186us 1 1 100.00
alert_handler_csr_rw 4.140s 129.842us 1 1 100.00
alert_handler_csr_aliasing 200.190s 45662.199us 1 1 100.00
alert_handler_same_csr_outstanding 16.890s 188.454us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 2.880s 80.186us 1 1 100.00
alert_handler_csr_rw 4.140s 129.842us 1 1 100.00
alert_handler_csr_aliasing 200.190s 45662.199us 1 1 100.00
alert_handler_same_csr_outstanding 16.890s 188.454us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 65.830s 881.004us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 65.830s 881.004us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 65.830s 881.004us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 65.830s 881.004us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 436.330s 59925.211us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 21.330s 3787.907us 1 1 100.00
alert_handler_tl_intg_err 32.100s 1255.005us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 32.100s 1255.005us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 65.830s 881.004us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 17.430s 303.405us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 17.430s 303.405us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 17.430s 303.405us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 17.430s 303.405us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 8.280s 595.675us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 622.240s 111268.587us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 8.280s 595.675us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1105.700s 16142.026us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1105.700s 16142.026us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 21.330s 3787.907us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 21.330s 3787.907us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 21.330s 3787.907us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 21.330s 3787.907us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 21.330s 3787.907us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 21.330s 3787.907us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 21.330s 3787.907us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 21.330s 3787.907us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 21.330s 3787.907us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 9.970s 2029.409us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:486) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state 1 test run
alert_handler_ping_timeout 2858840725347835290430890713185262897556580612651340967254484056642212403076 90
UVM_INFO @ 2182378800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped 1 test run
alert_handler_entropy_stress 101476948135276362681540500622959391553267966753055370290646539089420018889218 122
UVM_INFO @ 1049999004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
alert_handler_stress_all_with_rand_reset 92775094885563891249226420558067262598933883546021699903467846294939486389519 92
UVM_INFO @ 2029408531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---