Simulation Results: clkmgr

 
22/05/2026 03:08:15 DVSim: v1.49.0 sha: d71121d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 73.91 %
  • code
  • 67.44 %
  • assert
  • 88.43 %
  • func
  • 65.85 %
  • line
  • 81.41 %
  • branch
  • 86.53 %
  • cond
  • 75.41 %
  • toggle
  • 93.87 %
  • FSM
  • 0.00 %
Validation stages
V1
66.67%
V2
76.92%
V2S
37.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.170s 37.755us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 1.070s 59.752us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 1.260s 57.168us 1 1 100.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 4.910s 474.027us 0 1 0.00
csr_aliasing 0 1 0.00
clkmgr_csr_aliasing 0.950s 11.495us 0 1 0.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.550s 99.751us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 1 2 50.00
clkmgr_csr_rw 1.260s 57.168us 1 1 100.00
clkmgr_csr_aliasing 0.950s 11.495us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.830s 20.640us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.790s 118.810us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.760s 11.769us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.170s 37.755us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.690s 5.127us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.660s 3.877us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.690s 5.127us 0 1 0.00
stress_all 1 1 100.00
clkmgr_stress_all 1.330s 91.515us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 1.130s 47.081us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 3.750s 227.974us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 3.750s 227.974us 1 1 100.00
tl_d_outstanding_access 3 4 75.00
clkmgr_csr_hw_reset 1.070s 59.752us 1 1 100.00
clkmgr_csr_rw 1.260s 57.168us 1 1 100.00
clkmgr_csr_aliasing 0.950s 11.495us 0 1 0.00
clkmgr_same_csr_outstanding 1.010s 47.197us 1 1 100.00
tl_d_partial_access 3 4 75.00
clkmgr_csr_hw_reset 1.070s 59.752us 1 1 100.00
clkmgr_csr_rw 1.260s 57.168us 1 1 100.00
clkmgr_csr_aliasing 0.950s 11.495us 0 1 0.00
clkmgr_same_csr_outstanding 1.010s 47.197us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
clkmgr_sec_cm 1.460s 86.430us 0 1 0.00
clkmgr_tl_intg_err 0.750s 3.631us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.750s 106.510us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.750s 106.510us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.750s 106.510us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.750s 106.510us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.770s 3.543us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 0.750s 3.631us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.690s 5.127us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.660s 3.877us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.750s 106.510us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.510s 94.577us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 1.260s 57.168us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 1.460s 86.430us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 1.260s 57.168us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 1.260s 57.168us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 1.460s 86.430us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.680s 1.932us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 1.820s 117.994us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b* 2 test runs
clkmgr_frequency_timeout 110355456209510080159588159130933557777852979940054042725650170880930355285905 78
UVM_INFO @ 3876679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 25077607639471015031066828466631307692459000558350237969569858718118574210857 79
UVM_INFO @ 117993972 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * 2 test runs
clkmgr_tl_intg_err 13534010594812369224443318404006824718047502808690231053717099670743852455123 75
UVM_INFO @ 3631183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_aliasing 35980521108382960094662280835442323757564755405497482694641037621814819465702 75
UVM_INFO @ 11495134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* 1 test run
clkmgr_frequency 81598083182972030372512283211589731793179647241136859489156571137881061309500 75
UVM_INFO @ 5127111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_en 1 test run
clkmgr_regwen 18085813840936457219715178857633639025622140719448747395463879990363846283684 74
UVM_INFO @ 1931861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: * 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 57012126693089731253059573825111973404441186052428845199538097219751666774097 75
UVM_INFO @ 3542675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1047) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles. 1 test run
clkmgr_sec_cm 22832297371826369211028715601927192471082584343700931202906850005937322471159 108
UVM_INFO @ 86429608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: * 1 test run
clkmgr_csr_bit_bash 39145733745565344672463193363044842950128267304088052727469207717386339862768 75
UVM_INFO @ 474026571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---