Simulation Results: csrng

 
22/05/2026 03:08:15 DVSim: v1.49.0 sha: d71121d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 86.28 %
  • code
  • 92.21 %
  • assert
  • 94.54 %
  • func
  • 72.10 %
  • block
  • 96.85 %
  • line
  • 97.62 %
  • branch
  • 92.26 %
  • toggle
  • 93.24 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
91.67%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 3.000s 45.284us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 37.881us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 1.000s 16.041us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 7.000s 139.077us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 5.000s 167.243us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 1.000s 15.144us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 1.000s 16.041us 1 1 100.00
csrng_csr_aliasing 5.000s 167.243us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 5.000s 213.142us 1 1 100.00
alerts 1 1 100.00
csrng_alert 4.000s 110.288us 1 1 100.00
err 1 1 100.00
csrng_err 2.000s 33.742us 1 1 100.00
cmds 0 1 0.00
csrng_cmds 7.000s 384.864us 0 1 0.00
life cycle 0 1 0.00
csrng_cmds 7.000s 384.864us 0 1 0.00
stress_all 1 1 100.00
csrng_stress_all 89.000s 8009.014us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 2.000s 48.964us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 3.000s 25.261us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 5.000s 124.340us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 5.000s 124.340us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 2.000s 37.881us 1 1 100.00
csrng_csr_rw 1.000s 16.041us 1 1 100.00
csrng_csr_aliasing 5.000s 167.243us 1 1 100.00
csrng_same_csr_outstanding 2.000s 20.135us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 2.000s 37.881us 1 1 100.00
csrng_csr_rw 1.000s 16.041us 1 1 100.00
csrng_csr_aliasing 5.000s 167.243us 1 1 100.00
csrng_same_csr_outstanding 2.000s 20.135us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 3.000s 98.098us 1 1 100.00
csrng_tl_intg_err 4.000s 177.362us 1 1 100.00
sec_cm_config_regwen 1 2 50.00
csrng_regwen 1.000s 5.436us 0 1 0.00
csrng_csr_rw 1.000s 16.041us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 4.000s 110.288us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 89.000s 8009.014us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 5.000s 213.142us 1 1 100.00
csrng_err 2.000s 33.742us 1 1 100.00
csrng_sec_cm 3.000s 98.098us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 5.000s 213.142us 1 1 100.00
csrng_err 2.000s 33.742us 1 1 100.00
csrng_sec_cm 3.000s 98.098us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 5.000s 213.142us 1 1 100.00
csrng_err 2.000s 33.742us 1 1 100.00
csrng_sec_cm 3.000s 98.098us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 5.000s 213.142us 1 1 100.00
csrng_err 2.000s 33.742us 1 1 100.00
csrng_sec_cm 3.000s 98.098us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 5.000s 213.142us 1 1 100.00
csrng_err 2.000s 33.742us 1 1 100.00
csrng_sec_cm 3.000s 98.098us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 4.000s 110.288us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 5.000s 213.142us 1 1 100.00
csrng_err 2.000s 33.742us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 89.000s 8009.014us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 4.000s 110.288us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 4.000s 177.362us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 5.000s 213.142us 1 1 100.00
csrng_err 2.000s 33.742us 1 1 100.00
csrng_sec_cm 3.000s 98.098us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 5.000s 213.142us 1 1 100.00
csrng_err 2.000s 33.742us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 5.000s 213.142us 1 1 100.00
csrng_err 2.000s 33.742us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 5.000s 213.142us 1 1 100.00
csrng_err 2.000s 33.742us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 5.000s 213.142us 1 1 100.00
csrng_err 2.000s 33.742us 1 1 100.00
csrng_sec_cm 3.000s 98.098us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 5.000s 213.142us 1 1 100.00
csrng_err 2.000s 33.742us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 10802.053s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:671) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*]) 1 test run
csrng_cmds 38579976194469962058819445700637118856767952872662937678986303509193103139708 100
UVM_INFO @ 384864495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csrng_regwen_vseq.sv:67) virtual_sequencer [csrng_regwen_vseq] Was unable to flip INT_STATE_READ_ENABLE 1 test run
csrng_regwen 51499218552391641630672322535835212086462735874992692234152683335357300130651 99
UVM_INFO @ 5436276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
csrng_stress_all_with_rand_reset 31862925834952598359764360636063164630735169693652352740471215796451863366018 None