Simulation Results: dma

 
22/05/2026 03:08:15 DVSim: v1.49.0 sha: d71121d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 84.48 %
  • code
  • 91.82 %
  • assert
  • 96.50 %
  • func
  • 65.13 %
  • block
  • 97.34 %
  • line
  • 96.85 %
  • branch
  • 95.76 %
  • toggle
  • 83.12 %
  • FSM
  • 91.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 5.000s 1891.840us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 6.000s 432.058us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 5.000s 305.245us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 2.000s 318.668us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 1.000s 51.810us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 8.000s 738.063us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 4.000s 85.474us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 1.000s 92.702us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 1.000s 51.810us 1 1 100.00
dma_csr_aliasing 4.000s 85.474us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 39.000s 3316.609us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 227.000s 92046.220us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 478.000s 94231.201us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 478.000s 94231.201us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 227.000s 92046.220us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 484.000s 40145.629us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 478.000s 94231.201us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 10.000s 701.329us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 259.000s 20562.633us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 1.000s 16.929us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 1.000s 14.201us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 2.000s 315.217us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 2.000s 315.217us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 2.000s 318.668us 1 1 100.00
dma_csr_rw 1.000s 51.810us 1 1 100.00
dma_csr_aliasing 4.000s 85.474us 1 1 100.00
dma_same_csr_outstanding 2.000s 59.900us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 2.000s 318.668us 1 1 100.00
dma_csr_rw 1.000s 51.810us 1 1 100.00
dma_csr_aliasing 4.000s 85.474us 1 1 100.00
dma_same_csr_outstanding 2.000s 59.900us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 20.000s 2172.747us 1 1 100.00
dma_generic_stress 484.000s 40145.629us 1 1 100.00
dma_handshake_stress 478.000s 94231.201us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 5.000s 1852.497us 1 1 100.00
tl_intg_err 2 2 100.00
dma_tl_intg_err 2.000s 394.985us 1 1 100.00
dma_sec_cm 1.000s 11.813us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 53.000s 16143.595us 1 1 100.00
dma_longer_transfer 7.000s 335.749us 1 1 100.00
dma_stress_all_with_rand_reset 2.000s 1548.903us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1287) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
dma_stress_all_with_rand_reset 44837317309844651207292534069030937801117471950807009663206385676897448538268 96
UVM_INFO @ 1548902702ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---