Simulation Results: edn/edn0

 
22/05/2026 03:08:15 DVSim: v1.49.0 sha: d71121d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 76.79 %
  • code
  • 85.03 %
  • assert
  • 96.24 %
  • func
  • 49.09 %
  • block
  • 94.56 %
  • line
  • 97.27 %
  • branch
  • 88.20 %
  • toggle
  • 70.14 %
  • FSM
  • 84.50 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.000s 20.395us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.000s 16.834us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.000s 50.375us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.000s 37.194us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 2.000s 40.625us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.000s 37.333us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.000s 50.375us 1 1 100.00
edn_csr_aliasing 2.000s 40.625us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.000s 47.142us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.000s 47.142us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.000s 47.142us 1 1 100.00
interrupts 1 1 100.00
edn_intr 2.000s 22.448us 1 1 100.00
alerts 1 1 100.00
edn_alert 2.000s 84.581us 1 1 100.00
errs 1 1 100.00
edn_err 1.000s 80.483us 1 1 100.00
disable 2 2 100.00
edn_disable 1.000s 12.863us 1 1 100.00
edn_disable_auto_req_mode 1.000s 73.233us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 4.000s 573.787us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 1.000s 41.496us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 2.000s 78.385us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.000s 29.308us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.000s 29.308us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.000s 16.834us 1 1 100.00
edn_csr_rw 1.000s 50.375us 1 1 100.00
edn_csr_aliasing 2.000s 40.625us 1 1 100.00
edn_same_csr_outstanding 2.000s 40.859us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.000s 16.834us 1 1 100.00
edn_csr_rw 1.000s 50.375us 1 1 100.00
edn_csr_aliasing 2.000s 40.625us 1 1 100.00
edn_same_csr_outstanding 2.000s 40.859us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 7.000s 554.945us 1 1 100.00
edn_tl_intg_err 2.000s 186.622us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 2.000s 142.250us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 2.000s 84.581us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 7.000s 554.945us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 7.000s 554.945us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 7.000s 554.945us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 7.000s 554.945us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 2.000s 84.581us 1 1 100.00
edn_sec_cm 7.000s 554.945us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 2.000s 84.581us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.000s 186.622us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 47.000s 6459.092us 1 1 100.00