Simulation Results: edn/edn1

 
22/05/2026 03:08:15 DVSim: v1.49.0 sha: d71121d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.33 %
  • code
  • 82.73 %
  • assert
  • 98.18 %
  • func
  • 81.09 %
  • line
  • 98.18 %
  • branch
  • 93.29 %
  • cond
  • 90.08 %
  • toggle
  • 87.80 %
  • FSM
  • 44.32 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.870s 59.239us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.840s 14.814us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.770s 26.562us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.290s 223.136us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.230s 145.405us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 0.990s 28.998us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.770s 26.562us 1 1 100.00
edn_csr_aliasing 1.230s 145.405us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 0.960s 55.346us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 0.960s 55.346us 1 1 100.00
genbits 1 1 100.00
edn_genbits 0.960s 55.346us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.840s 27.627us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.910s 100.349us 1 1 100.00
errs 1 1 100.00
edn_err 0.990s 57.451us 1 1 100.00
disable 2 2 100.00
edn_disable 0.880s 14.028us 1 1 100.00
edn_disable_auto_req_mode 1.000s 118.927us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.610s 294.126us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.750s 13.041us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.940s 17.775us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.860s 74.573us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.860s 74.573us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.840s 14.814us 1 1 100.00
edn_csr_rw 0.770s 26.562us 1 1 100.00
edn_csr_aliasing 1.230s 145.405us 1 1 100.00
edn_same_csr_outstanding 0.940s 100.192us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.840s 14.814us 1 1 100.00
edn_csr_rw 0.770s 26.562us 1 1 100.00
edn_csr_aliasing 1.230s 145.405us 1 1 100.00
edn_same_csr_outstanding 0.940s 100.192us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 1.930s 276.206us 1 1 100.00
edn_tl_intg_err 1.820s 176.273us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.950s 20.997us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.910s 100.349us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 1.930s 276.206us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 1.930s 276.206us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 1.930s 276.206us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 1.930s 276.206us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.910s 100.349us 1 1 100.00
edn_sec_cm 1.930s 276.206us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.910s 100.349us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.820s 176.273us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 71.120s 16998.100us 1 1 100.00