Simulation Results: entropy_src/rng_16bits

 
22/05/2026 03:08:15 DVSim: v1.49.0 sha: d71121d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 66.59 %
  • code
  • 80.04 %
  • assert
  • 73.36 %
  • func
  • 46.38 %
  • block
  • 93.85 %
  • line
  • 97.55 %
  • branch
  • 85.46 %
  • toggle
  • 52.77 %
  • FSM
  • 84.38 %
Validation stages
V1
83.33%
V2
93.75%
V2S
85.71%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
entropy_src_smoke 3.000s 217.944us 1 1 100.00
csr_hw_reset 1 1 100.00
entropy_src_csr_hw_reset 2.000s 435.553us 1 1 100.00
csr_rw 1 1 100.00
entropy_src_csr_rw 2.000s 93.406us 1 1 100.00
csr_bit_bash 1 1 100.00
entropy_src_csr_bit_bash 15.000s 855.695us 1 1 100.00
csr_aliasing 1 1 100.00
entropy_src_csr_aliasing 4.000s 408.223us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
entropy_src_csr_mem_rw_with_rand_reset 1.000s 14.469us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
entropy_src_csr_rw 2.000s 93.406us 1 1 100.00
entropy_src_csr_aliasing 4.000s 408.223us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 2 3 66.67
entropy_src_smoke 3.000s 217.944us 1 1 100.00
entropy_src_rng 296.000s 14040.863us 1 1 100.00
entropy_src_fw_ov 305.000s 13034.095us 0 1 0.00
firmware_mode 0 1 0.00
entropy_src_fw_ov 305.000s 13034.095us 0 1 0.00
rng_mode 1 1 100.00
entropy_src_rng 296.000s 14040.863us 1 1 100.00
rng_max_rate 1 1 100.00
entropy_src_rng_max_rate 71.000s 13082.571us 1 1 100.00
health_checks 1 1 100.00
entropy_src_rng 296.000s 14040.863us 1 1 100.00
conditioning 1 1 100.00
entropy_src_rng 296.000s 14040.863us 1 1 100.00
interrupts 2 2 100.00
entropy_src_rng 296.000s 14040.863us 1 1 100.00
entropy_src_intr 12.000s 3081.810us 1 1 100.00
alerts 2 2 100.00
entropy_src_rng 296.000s 14040.863us 1 1 100.00
entropy_src_functional_alerts 6.000s 720.937us 1 1 100.00
stress_all 1 1 100.00
entropy_src_stress_all 76.000s 13843.014us 1 1 100.00
functional_errors 1 1 100.00
entropy_src_functional_errors 2.000s 65.059us 1 1 100.00
firmware_ov_read_contiguous_data 1 1 100.00
entropy_src_fw_ov_contiguous 11.000s 200.614us 1 1 100.00
intr_test 1 1 100.00
entropy_src_intr_test 1.000s 45.211us 1 1 100.00
alert_test 1 1 100.00
entropy_src_alert_test 2.000s 30.447us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
entropy_src_tl_errors 2.000s 248.332us 1 1 100.00
tl_d_illegal_access 1 1 100.00
entropy_src_tl_errors 2.000s 248.332us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 435.553us 1 1 100.00
entropy_src_csr_rw 2.000s 93.406us 1 1 100.00
entropy_src_csr_aliasing 4.000s 408.223us 1 1 100.00
entropy_src_same_csr_outstanding 3.000s 174.989us 1 1 100.00
tl_d_partial_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 435.553us 1 1 100.00
entropy_src_csr_rw 2.000s 93.406us 1 1 100.00
entropy_src_csr_aliasing 4.000s 408.223us 1 1 100.00
entropy_src_same_csr_outstanding 3.000s 174.989us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
entropy_src_sec_cm 2.000s 55.549us 1 1 100.00
entropy_src_tl_intg_err 4.000s 1516.052us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
entropy_src_rng 296.000s 14040.863us 1 1 100.00
entropy_src_cfg_regwen 2.000s 15.439us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
entropy_src_rng 296.000s 14040.863us 1 1 100.00
sec_cm_config_redun 1 1 100.00
entropy_src_rng 296.000s 14040.863us 1 1 100.00
sec_cm_intersig_mubi 1 2 50.00
entropy_src_rng 296.000s 14040.863us 1 1 100.00
entropy_src_fw_ov 305.000s 13034.095us 0 1 0.00
sec_cm_main_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 65.059us 1 1 100.00
entropy_src_sec_cm 2.000s 55.549us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 65.059us 1 1 100.00
entropy_src_sec_cm 2.000s 55.549us 1 1 100.00
sec_cm_rng_bkgn_chk 1 1 100.00
entropy_src_rng 296.000s 14040.863us 1 1 100.00
sec_cm_fifo_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 65.059us 1 1 100.00
entropy_src_sec_cm 2.000s 55.549us 1 1 100.00
sec_cm_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 65.059us 1 1 100.00
entropy_src_sec_cm 2.000s 55.549us 1 1 100.00
sec_cm_ctr_local_esc 1 1 100.00
entropy_src_functional_errors 2.000s 65.059us 1 1 100.00
sec_cm_esfinal_rdata_bus_consistency 1 1 100.00
entropy_src_functional_alerts 6.000s 720.937us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
entropy_src_tl_intg_err 4.000s 1516.052us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
external_health_tests 1 1 100.00
entropy_src_rng_with_xht_rsps 17.000s 14038.983us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:354) scoreboard [scoreboard] alert recov_alert did not trigger max_delay:* 1 test run
entropy_src_fw_ov 54937658784765058192359656939445203269762376571485363382990503480433507402891 2135
UVM_INFO @ 13034094827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (entropy_src_base_vseq.sv:83) virtual_sequencer [mirror] Failed to mirror adaptp_hi_total_fails 1 test run
entropy_src_csr_mem_rw_with_rand_reset 77073502603935894997610496962712040304064167279420031478987599006650264541090 113
UVM_INFO @ 14468551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---