Simulation Results: hmac

 
22/05/2026 03:08:15 DVSim: v1.49.0 sha: d71121d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 74.18 %
  • code
  • 96.08 %
  • assert
  • 97.17 %
  • func
  • 29.28 %
  • block
  • 97.64 %
  • line
  • 98.44 %
  • branch
  • 94.11 %
  • toggle
  • 96.96 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 2.000s 147.903us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 1.000s 82.196us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 1.000s 21.483us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 7.000s 860.726us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 5.000s 1317.861us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 2.000s 27.564us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 1.000s 21.483us 1 1 100.00
hmac_csr_aliasing 5.000s 1317.861us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 32.000s 781.333us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 25.000s 1040.523us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 10.000s 204.946us 1 1 100.00
hmac_test_sha384_vectors 20.000s 257.174us 1 1 100.00
hmac_test_sha512_vectors 21.000s 1056.772us 1 1 100.00
hmac_test_hmac256_vectors 7.000s 890.253us 1 1 100.00
hmac_test_hmac384_vectors 14.000s 3629.854us 1 1 100.00
hmac_test_hmac512_vectors 10.000s 581.453us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 17.000s 1640.281us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 195.000s 22616.070us 1 1 100.00
error 1 1 100.00
hmac_error 96.000s 10192.685us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 82.000s 19107.629us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 2.000s 147.903us 1 1 100.00
hmac_long_msg 32.000s 781.333us 1 1 100.00
hmac_back_pressure 25.000s 1040.523us 1 1 100.00
hmac_datapath_stress 195.000s 22616.070us 1 1 100.00
hmac_burst_wr 17.000s 1640.281us 1 1 100.00
hmac_stress_all 67.000s 5209.082us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 2.000s 147.903us 1 1 100.00
hmac_long_msg 32.000s 781.333us 1 1 100.00
hmac_back_pressure 25.000s 1040.523us 1 1 100.00
hmac_datapath_stress 195.000s 22616.070us 1 1 100.00
hmac_wipe_secret 82.000s 19107.629us 1 1 100.00
hmac_test_sha256_vectors 10.000s 204.946us 1 1 100.00
hmac_test_sha384_vectors 20.000s 257.174us 1 1 100.00
hmac_test_sha512_vectors 21.000s 1056.772us 1 1 100.00
hmac_test_hmac256_vectors 7.000s 890.253us 1 1 100.00
hmac_test_hmac384_vectors 14.000s 3629.854us 1 1 100.00
hmac_test_hmac512_vectors 10.000s 581.453us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 2.000s 147.903us 1 1 100.00
hmac_long_msg 32.000s 781.333us 1 1 100.00
hmac_back_pressure 25.000s 1040.523us 1 1 100.00
hmac_datapath_stress 195.000s 22616.070us 1 1 100.00
hmac_burst_wr 17.000s 1640.281us 1 1 100.00
hmac_error 96.000s 10192.685us 1 1 100.00
hmac_wipe_secret 82.000s 19107.629us 1 1 100.00
hmac_test_sha256_vectors 10.000s 204.946us 1 1 100.00
hmac_test_sha384_vectors 20.000s 257.174us 1 1 100.00
hmac_test_sha512_vectors 21.000s 1056.772us 1 1 100.00
hmac_test_hmac256_vectors 7.000s 890.253us 1 1 100.00
hmac_test_hmac384_vectors 14.000s 3629.854us 1 1 100.00
hmac_test_hmac512_vectors 10.000s 581.453us 1 1 100.00
hmac_stress_all 67.000s 5209.082us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 67.000s 5209.082us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 2.000s 58.995us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 2.000s 33.343us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.000s 74.300us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.000s 74.300us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 1.000s 82.196us 1 1 100.00
hmac_csr_rw 1.000s 21.483us 1 1 100.00
hmac_csr_aliasing 5.000s 1317.861us 1 1 100.00
hmac_same_csr_outstanding 2.000s 31.740us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 1.000s 82.196us 1 1 100.00
hmac_csr_rw 1.000s 21.483us 1 1 100.00
hmac_csr_aliasing 5.000s 1317.861us 1 1 100.00
hmac_same_csr_outstanding 2.000s 31.740us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.000s 283.699us 1 1 100.00
hmac_tl_intg_err 2.000s 369.056us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.000s 369.056us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 2.000s 147.903us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 3.000s 123.231us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 208.000s 13454.040us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 4.000s 545.480us 1 1 100.00