Simulation Results

Simulation Results: i2c

22/05/2026 03:08:15 DVSim: v1.49.0 sha: d71121d json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
88.47 %

code
89.12 %

assert
97.04 %

func
79.24 %

block
95.90 %

line
95.34 %

branch
92.63 %

toggle
86.51 %

FSM
82.01 %

Validation stages

V1		100.00%
V2		82.93%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	96.000s	7344.612us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	10.000s	3957.908us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	1.000s	84.245us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	2.000s	19.223us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	3.000s	146.672us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	2.000s	64.411us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	1.000s	31.963us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	2.000s	19.223us	1	1	100.00
	i2c_csr_aliasing	2.000s	64.411us	1	1	100.00

34/41 passed

82.93 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	1.000s	15.830us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	242.000s	31110.696us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	63.000s	7367.423us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	2.000s	47.739us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	2218.000s	10806.692us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	1430.000s	13620.525us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	2.000s	191.704us	1	1	100.00
	i2c_host_fifo_fmt_empty	11.000s	421.432us	1	1	100.00
	i2c_host_fifo_reset_rx	3.000s	389.702us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	76.000s	1732.758us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	5.000s	377.688us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	3.000s	113.494us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	4.000s	2209.317us	0	1	0.00
target_stress_all				0	1	0.00
	i2c_target_stress_all	3600.000s	0.000us	0	1	0.00
target_maxperf				1	1	100.00
	i2c_target_perf	4.000s	1348.502us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	19.000s	1488.931us	1	1	100.00
	i2c_target_intr_smoke	6.000s	1021.753us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	2.000s	323.032us	1	1	100.00
	i2c_target_fifo_reset_tx	3.000s	599.813us	1	1	100.00
target_fifo_full				1	3	33.33
	i2c_target_stress_wr	3601.000s	0.000us	0	1	0.00
	i2c_target_stress_rd	19.000s	1488.931us	1	1	100.00
	i2c_target_intr_stress_wr	3602.211s	0.000us	0	1	0.00
target_timeout				1	1	100.00
	i2c_target_timeout	7.000s	5699.940us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	3.000s	1051.520us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	8.000s	14481.548us	1	1	100.00
target_mode_glitch				1	1	100.00
	i2c_target_hrst	3.000s	224.884us	1	1	100.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	3.000s	381.044us	1	1	100.00
	i2c_target_fifo_watermarks_tx	3.000s	169.056us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	63.000s	7367.423us	1	1	100.00
	i2c_host_perf_precise	20.000s	2541.457us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	5.000s	377.688us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	4.000s	113.154us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	4.000s	2073.628us	1	1	100.00
	i2c_target_nack_acqfull_addr	3.000s	1870.950us	1	1	100.00
	i2c_target_nack_txstretch	4.000s	219.394us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	5.000s	381.844us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	3.000s	1530.255us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	1.000s	18.507us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	1.000s	18.253us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	2.000s	348.611us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	2.000s	348.611us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	1.000s	84.245us	1	1	100.00
	i2c_csr_rw	2.000s	19.223us	1	1	100.00
	i2c_csr_aliasing	2.000s	64.411us	1	1	100.00
	i2c_same_csr_outstanding	2.000s	211.583us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	1.000s	84.245us	1	1	100.00
	i2c_csr_rw	2.000s	19.223us	1	1	100.00
	i2c_csr_aliasing	2.000s	64.411us	1	1	100.00
	i2c_same_csr_outstanding	2.000s	211.583us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	2.000s	206.010us	1	1	100.00
	i2c_sec_cm	1.000s	378.382us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	2.000s	206.010us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	17.000s	1954.912us	1
target_error_intr				1
	i2c_target_unexp_stop	2.000s	135.407us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	22.000s	1483.534us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				3 test runs
	i2c_host_error_intr	66933117008379762949308242007442461965469606195084714497165036588623255323423	89	UVM_INFO @ 15830186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_stress_all	63306302600440146351178042375442532522532439518767548461263717869751949301455	148	UVM_INFO @ 31110695720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	15627196652921847609515644395252514922792145952789652140944034241095026488639	132	UVM_INFO @ 1483533903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				3 test runs
	i2c_target_stress_wr	16760162446556484646042148854211524828725715616069263220395161810270933977396	None
	i2c_target_intr_stress_wr	28197763675429617927544563409436128515211080125840217472608462437674053467775	None
	i2c_target_stress_all	40928278506640406493728311961559228244394586881439782223779708068835144198044	None
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	107207601197271876458821081446548484526746153182477457710548600395086348174925	93	UVM_INFO @ 2209316543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])				1 test run
	i2c_target_unexp_stop	45305191737070964346317161447464015783059412679298035900200487461159433327303	87	UVM_INFO @ 135407482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1287) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				1 test run
	i2c_host_stress_all_with_rand_reset	98616451813790198124126328934018790553607443131318109037902485573350937162076	98	UVM_INFO @ 1954911782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared:				1 test run
	i2c_host_mode_toggle	74879614863192217889106934420082252932048790217233112125841088356918176854027	94	---------------------------------------------------- Name Type Size Value ---------------------------------------------------- mon_dut_item i2c_item - @17445