Simulation Results: kmac/masked

 
22/05/2026 03:08:15 DVSim: v1.49.0 sha: d71121d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.68 %
  • code
  • 90.09 %
  • assert
  • 97.98 %
  • func
  • 92.98 %
  • line
  • 98.96 %
  • branch
  • 96.13 %
  • cond
  • 90.85 %
  • toggle
  • 99.70 %
  • FSM
  • 64.79 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 44.670s 6782.824us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 1.050s 27.232us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 1.350s 32.320us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 15.940s 5229.409us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 3.710s 217.459us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 2.030s 93.945us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 1.350s 32.320us 1 1 100.00
kmac_csr_aliasing 3.710s 217.459us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.820s 14.512us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.610s 104.725us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 1732.840s 63738.732us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 737.940s 99785.613us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 26.080s 1727.233us 1 1 100.00
kmac_test_vectors_sha3_256 33.250s 2819.245us 1 1 100.00
kmac_test_vectors_sha3_384 26.180s 8128.528us 1 1 100.00
kmac_test_vectors_sha3_512 16.480s 7301.453us 1 1 100.00
kmac_test_vectors_shake_128 133.820s 9692.372us 1 1 100.00
kmac_test_vectors_shake_256 113.680s 46026.165us 1 1 100.00
kmac_test_vectors_kmac 2.550s 90.521us 1 1 100.00
kmac_test_vectors_kmac_xof 4.230s 191.951us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 358.320s 74494.261us 1 1 100.00
app 1 1 100.00
kmac_app 201.280s 5050.582us 1 1 100.00
app_with_partial_data 1 1 100.00
kmac_app_with_partial_data 180.610s 4205.544us 1 1 100.00
entropy_refresh 1 1 100.00
kmac_entropy_refresh 197.350s 11154.086us 1 1 100.00
error 1 1 100.00
kmac_error 108.340s 6482.030us 1 1 100.00
key_error 1 1 100.00
kmac_key_error 7.970s 5500.398us 1 1 100.00
sideload_invalid 1 1 100.00
kmac_sideload_invalid 5.050s 1085.939us 1 1 100.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 0.980s 39.052us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 13.760s 283.798us 1 1 100.00
entropy_ready_error 1 1 100.00
kmac_entropy_ready_error 51.620s 13286.873us 1 1 100.00
lc_escalation 1 1 100.00
kmac_lc_escalation 1.550s 85.112us 1 1 100.00
stress_all 1 1 100.00
kmac_stress_all 343.720s 60701.941us 1 1 100.00
intr_test 1 1 100.00
kmac_intr_test 1.060s 13.705us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 0.980s 17.878us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 3.510s 385.395us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 3.510s 385.395us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 1.050s 27.232us 1 1 100.00
kmac_csr_rw 1.350s 32.320us 1 1 100.00
kmac_csr_aliasing 3.710s 217.459us 1 1 100.00
kmac_same_csr_outstanding 1.780s 125.698us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 1.050s 27.232us 1 1 100.00
kmac_csr_rw 1.350s 32.320us 1 1 100.00
kmac_csr_aliasing 3.710s 217.459us 1 1 100.00
kmac_same_csr_outstanding 1.780s 125.698us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 1.980s 148.292us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 1.980s 148.292us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 1.980s 148.292us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 1.980s 148.292us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 2.710s 48.552us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_sec_cm 39.960s 4245.132us 1 1 100.00
kmac_tl_intg_err 2.810s 257.219us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 2.810s 257.219us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 1.550s 85.112us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 44.670s 6782.824us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 358.320s 74494.261us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 1.980s 148.292us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 39.960s 4245.132us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 39.960s 4245.132us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 39.960s 4245.132us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 44.670s 6782.824us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 1.550s 85.112us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 39.960s 4245.132us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 1 1 100.00
kmac_mubi 288.250s 32640.417us 1 1 100.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 44.670s 6782.824us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
kmac_stress_all_with_rand_reset 10.840s 2977.702us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:858) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) 1 test run
kmac_stress_all_with_rand_reset 38913061561879031806448245391301200405767823794047815526361831797517965233105 197
UVM_INFO @ 2977701508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---