Simulation Results: kmac/unmasked

 
22/05/2026 03:08:15 DVSim: v1.49.0 sha: d71121d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.59 %
  • code
  • 88.35 %
  • assert
  • 98.65 %
  • func
  • 90.76 %
  • line
  • 97.15 %
  • branch
  • 94.42 %
  • cond
  • 91.53 %
  • toggle
  • 99.96 %
  • FSM
  • 58.68 %
Validation stages
V1
100.00%
V2
96.55%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 15.200s 383.418us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 1.200s 58.805us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 1.100s 25.416us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 8.980s 9276.861us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 5.360s 140.116us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 1.910s 70.932us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 1.100s 25.416us 1 1 100.00
kmac_csr_aliasing 5.360s 140.116us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 1.020s 36.890us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.430s 22.904us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 54.660s 3665.543us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 333.450s 31810.686us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 33.530s 2667.556us 1 1 100.00
kmac_test_vectors_sha3_256 36.830s 10790.402us 1 1 100.00
kmac_test_vectors_sha3_384 1244.440s 363592.785us 1 1 100.00
kmac_test_vectors_sha3_512 10.790s 1140.871us 1 1 100.00
kmac_test_vectors_shake_128 151.580s 66532.841us 1 1 100.00
kmac_test_vectors_shake_256 76.300s 8165.889us 1 1 100.00
kmac_test_vectors_kmac 3.530s 412.590us 1 1 100.00
kmac_test_vectors_kmac_xof 2.150s 101.683us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 114.620s 24680.996us 1 1 100.00
app 1 1 100.00
kmac_app 113.140s 18537.905us 1 1 100.00
app_with_partial_data 1 1 100.00
kmac_app_with_partial_data 97.530s 11000.076us 1 1 100.00
entropy_refresh 1 1 100.00
kmac_entropy_refresh 183.600s 16789.678us 1 1 100.00
error 1 1 100.00
kmac_error 226.660s 16554.607us 1 1 100.00
key_error 1 1 100.00
kmac_key_error 5.720s 1571.273us 1 1 100.00
sideload_invalid 0 1 0.00
kmac_sideload_invalid 89.830s 10041.136us 0 1 0.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 30.120s 2022.816us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 16.160s 3207.900us 1 1 100.00
entropy_ready_error 1 1 100.00
kmac_entropy_ready_error 38.090s 6513.163us 1 1 100.00
lc_escalation 1 1 100.00
kmac_lc_escalation 1.620s 91.529us 1 1 100.00
stress_all 1 1 100.00
kmac_stress_all 16.810s 585.557us 1 1 100.00
intr_test 1 1 100.00
kmac_intr_test 1.010s 15.433us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 1.110s 72.241us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 1.780s 35.551us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 1.780s 35.551us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 1.200s 58.805us 1 1 100.00
kmac_csr_rw 1.100s 25.416us 1 1 100.00
kmac_csr_aliasing 5.360s 140.116us 1 1 100.00
kmac_same_csr_outstanding 1.580s 324.486us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 1.200s 58.805us 1 1 100.00
kmac_csr_rw 1.100s 25.416us 1 1 100.00
kmac_csr_aliasing 5.360s 140.116us 1 1 100.00
kmac_same_csr_outstanding 1.580s 324.486us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 1.280s 102.352us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 1.280s 102.352us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 1.280s 102.352us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 1.280s 102.352us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 2.540s 182.592us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_sec_cm 24.830s 5048.487us 1 1 100.00
kmac_tl_intg_err 3.700s 98.289us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 3.700s 98.289us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 1.620s 91.529us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 15.200s 383.418us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 114.620s 24680.996us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 1.280s 102.352us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 24.830s 5048.487us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 24.830s 5048.487us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 24.830s 5048.487us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 15.200s 383.418us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 1.620s 91.529us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 24.830s 5048.487us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 1 1 100.00
kmac_mubi 19.410s 1390.846us 1 1 100.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 15.200s 383.418us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
kmac_stress_all_with_rand_reset 49.340s 3739.062us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) 1 test run
kmac_sideload_invalid 78387730198019836788805107120546070957777862157161344052749338447027383743594 82
UVM_INFO @ 10041136024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
kmac_stress_all_with_rand_reset 96418696633428116296662860350016557056859364770910771460209511690681309264090 191
UVM_INFO @ 3739061563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---