Simulation Results: lc_ctrl/volatile_unlock_disabled

 
22/05/2026 03:08:15 DVSim: v1.49.0 sha: d71121d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.96 %
  • code
  • 93.28 %
  • assert
  • 95.97 %
  • func
  • 86.62 %
  • block
  • 96.70 %
  • line
  • 97.35 %
  • branch
  • 91.61 %
  • toggle
  • 88.93 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 63.907us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.000s 51.189us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.000s 166.104us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 972.134us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 3.000s 37.341us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.000s 95.368us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.000s 166.104us 1 1 100.00
lc_ctrl_csr_aliasing 3.000s 37.341us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 2.000s 241.725us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 4.000s 206.535us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.000s 88.868us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 3.000s 148.999us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 4.000s 3094.701us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 6.000s 270.012us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 4.000s 3094.701us 1 1 100.00
lc_ctrl_prog_failure 3.000s 148.999us 1 1 100.00
lc_ctrl_errors 6.000s 270.012us 1 1 100.00
lc_ctrl_security_escalation 7.000s 626.575us 1 1 100.00
lc_ctrl_jtag_state_failure 16.000s 1787.172us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.000s 1310.520us 1 1 100.00
lc_ctrl_jtag_errors 56.000s 16699.274us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 6.000s 3006.466us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.000s 415.391us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.000s 1310.520us 1 1 100.00
lc_ctrl_jtag_errors 56.000s 16699.274us 1 1 100.00
lc_ctrl_jtag_access 7.000s 3500.244us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 7.000s 858.152us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 4.000s 135.005us 1 1 100.00
lc_ctrl_jtag_csr_rw 3.000s 139.090us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 22.000s 5849.234us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 6.000s 1728.176us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 3.000s 51.452us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.000s 526.924us 1 1 100.00
lc_ctrl_jtag_alert_test 3.000s 159.027us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 4.000s 796.994us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 13.810us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 58.000s 3845.788us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 3.000s 20.863us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 92.195us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 92.195us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 51.189us 1 1 100.00
lc_ctrl_csr_rw 1.000s 166.104us 1 1 100.00
lc_ctrl_csr_aliasing 3.000s 37.341us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 88.324us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 51.189us 1 1 100.00
lc_ctrl_csr_rw 1.000s 166.104us 1 1 100.00
lc_ctrl_csr_aliasing 3.000s 37.341us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 88.324us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 3.000s 284.168us 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 67.019us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 67.019us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 4.000s 206.535us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 3094.701us 1 1 100.00
lc_ctrl_sec_cm 3.000s 284.168us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 3094.701us 1 1 100.00
lc_ctrl_sec_cm 3.000s 284.168us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 4.000s 3094.701us 1 1 100.00
lc_ctrl_sec_cm 3.000s 284.168us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 4.000s 3094.701us 1 1 100.00
lc_ctrl_sec_cm 3.000s 284.168us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 3094.701us 1 1 100.00
lc_ctrl_sec_cm 3.000s 284.168us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 3094.701us 1 1 100.00
lc_ctrl_sec_cm 3.000s 284.168us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 3094.701us 1 1 100.00
lc_ctrl_sec_cm 3.000s 284.168us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 4.000s 3094.701us 1 1 100.00
lc_ctrl_sec_cm 3.000s 284.168us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 7.000s 626.575us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 2.000s 241.725us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.000s 415.391us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.000s 2508.881us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.000s 2508.881us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.000s 320.887us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.000s 1605.902us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.000s 1605.902us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 53.000s 10842.478us 1 1 100.00