Simulation Results: lc_ctrl/volatile_unlock_enabled

 
22/05/2026 03:08:15 DVSim: v1.49.0 sha: d71121d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.25 %
  • code
  • 93.89 %
  • assert
  • 96.25 %
  • func
  • 86.62 %
  • block
  • 97.11 %
  • line
  • 97.63 %
  • branch
  • 92.68 %
  • toggle
  • 87.63 %
  • FSM
  • 97.62 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 41.024us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 15.192us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.000s 28.913us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 41.934us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 157.401us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.000s 27.623us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.000s 28.913us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 157.401us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 2.000s 211.988us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 6.000s 326.232us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 2.000s 11.822us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.000s 61.960us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 7.000s 1116.888us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 6.000s 228.001us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 7.000s 1116.888us 1 1 100.00
lc_ctrl_prog_failure 2.000s 61.960us 1 1 100.00
lc_ctrl_errors 6.000s 228.001us 1 1 100.00
lc_ctrl_security_escalation 8.000s 3010.012us 1 1 100.00
lc_ctrl_jtag_state_failure 12.000s 1938.592us 1 1 100.00
lc_ctrl_jtag_prog_failure 7.000s 392.657us 1 1 100.00
lc_ctrl_jtag_errors 8.000s 1110.279us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 14.000s 1231.261us 1 1 100.00
lc_ctrl_jtag_state_post_trans 10.000s 1106.484us 1 1 100.00
lc_ctrl_jtag_prog_failure 7.000s 392.657us 1 1 100.00
lc_ctrl_jtag_errors 8.000s 1110.279us 1 1 100.00
lc_ctrl_jtag_access 11.000s 2300.327us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 14.000s 889.075us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.000s 227.389us 1 1 100.00
lc_ctrl_jtag_csr_rw 3.000s 357.826us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 8.000s 1054.893us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 7.000s 552.535us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 3.000s 181.904us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 4.000s 174.616us 1 1 100.00
lc_ctrl_jtag_alert_test 2.000s 62.474us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 3.000s 1005.467us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.000s 31.859us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 86.000s 44582.560us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 28.446us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 86.595us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 86.595us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 15.192us 1 1 100.00
lc_ctrl_csr_rw 1.000s 28.913us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 157.401us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 45.860us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 15.192us 1 1 100.00
lc_ctrl_csr_rw 1.000s 28.913us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 157.401us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 45.860us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 3.000s 507.759us 1 1 100.00
lc_ctrl_tl_intg_err 1.000s 592.110us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.000s 592.110us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 6.000s 326.232us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 7.000s 1116.888us 1 1 100.00
lc_ctrl_sec_cm 3.000s 507.759us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 7.000s 1116.888us 1 1 100.00
lc_ctrl_sec_cm 3.000s 507.759us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.000s 1116.888us 1 1 100.00
lc_ctrl_sec_cm 3.000s 507.759us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.000s 1116.888us 1 1 100.00
lc_ctrl_sec_cm 3.000s 507.759us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 7.000s 1116.888us 1 1 100.00
lc_ctrl_sec_cm 3.000s 507.759us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.000s 1116.888us 1 1 100.00
lc_ctrl_sec_cm 3.000s 507.759us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.000s 1116.888us 1 1 100.00
lc_ctrl_sec_cm 3.000s 507.759us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 7.000s 1116.888us 1 1 100.00
lc_ctrl_sec_cm 3.000s 507.759us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 8.000s 3010.012us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 2.000s 211.988us 1 1 100.00
lc_ctrl_jtag_state_post_trans 10.000s 1106.484us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.000s 1073.859us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.000s 1073.859us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.000s 298.401us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.000s 1526.718us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.000s 1526.718us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 19.000s 5317.165us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 53429072731141880394797726148221057985582425329340694166610005965846698728136 464
UVM_INFO @ 5317165130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---