Simulation Results: mbx

 
22/05/2026 03:08:15 DVSim: v1.49.0 sha: d71121d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.74 %
  • code
  • 91.55 %
  • assert
  • 97.62 %
  • func
  • 77.04 %
  • block
  • 96.88 %
  • line
  • 96.71 %
  • branch
  • 91.89 %
  • toggle
  • 86.04 %
Validation stages
V1
83.33%
V2
81.82%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_smoke 1 1 100.00
mbx_smoke 35.000s 26065.371us 1 1 100.00
csr_hw_reset 1 1 100.00
mbx_csr_hw_reset 1.000s 38.707us 1 1 100.00
csr_rw 1 1 100.00
mbx_csr_rw 2.000s 36.096us 1 1 100.00
csr_bit_bash 1 1 100.00
mbx_csr_bit_bash 2.000s 43.022us 1 1 100.00
csr_aliasing 1 1 100.00
mbx_csr_aliasing 2.000s 34.963us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
mbx_csr_mem_rw_with_rand_reset 2.000s 2.020us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
mbx_csr_rw 2.000s 36.096us 1 1 100.00
mbx_csr_aliasing 2.000s 34.963us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_stress 1 1 100.00
mbx_stress 158.000s 19861.330us 1 1 100.00
mbx_max_activity 0 1 0.00
mbx_stress_zero_delays 4.000s 167.072us 0 1 0.00
mbx_imbx_oob 1 1 100.00
mbx_imbx_oob 18.000s 7041.920us 1 1 100.00
mbx_doe_intr_msg 1 1 100.00
mbx_doe_intr_msg 17.000s 566.893us 1 1 100.00
alert_test 1 1 100.00
mbx_alert_test 2.000s 18.492us 1 1 100.00
intr_test 1 1 100.00
mbx_intr_test 1.000s 129.783us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
mbx_tl_errors 1.000s 4.460us 0 1 0.00
tl_d_illegal_access 0 1 0.00
mbx_tl_errors 1.000s 4.460us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
mbx_csr_hw_reset 1.000s 38.707us 1 1 100.00
mbx_csr_rw 2.000s 36.096us 1 1 100.00
mbx_csr_aliasing 2.000s 34.963us 1 1 100.00
mbx_same_csr_outstanding 1.000s 184.738us 1 1 100.00
tl_d_partial_access 4 4 100.00
mbx_csr_hw_reset 1.000s 38.707us 1 1 100.00
mbx_csr_rw 2.000s 36.096us 1 1 100.00
mbx_csr_aliasing 2.000s 34.963us 1 1 100.00
mbx_same_csr_outstanding 1.000s 184.738us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
mbx_tl_intg_err 2.000s 208.551us 1 1 100.00
mbx_sec_cm 1.000s 19.487us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:582) scoreboard [scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted *, but saw *). 2 test runs
mbx_tl_errors 66708339882902607471346901221101844610871578379096901363137915919092942296100 85
TL item was: req: (cip_tl_seq_item@18947) { a_addr: 'h7e669650 a_data: 'hf08d4fd3 a_mask: 'h9 a_size: 'h2 a_param: 'h0 a_source: 'h1e a_opcode: 'h1 a_user: 'h27040 d_param: 'h0 d_source: 'h1e d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 4459854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
mbx_csr_mem_rw_with_rand_reset 27028539897832153427063186412983031351789551089908929005319065851152608133774 86
TL item was: req: (cip_tl_seq_item@19692) { a_addr: 'h8c576070 a_data: 'h3682bd64 a_mask: 'h2 a_size: 'h1 a_param: 'h0 a_source: 'hf1 a_opcode: 'h1 a_user: 'h25e78 d_param: 'h0 d_source: 'hf1 d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h10aa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 2019722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register 1 test run
mbx_stress_zero_delays 42558881070981026495534085011544485990569035460870942387211136034260114456516 126
UVM_INFO @ 167071614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---