Simulation Results: otbn

 
22/05/2026 03:08:15 DVSim: v1.49.0 sha: d71121d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.80 %
  • code
  • 95.34 %
  • assert
  • 90.33 %
  • func
  • 98.73 %
  • block
  • 99.41 %
  • line
  • 99.55 %
  • branch
  • 92.47 %
  • toggle
  • 91.76 %
  • FSM
  • 97.56 %
Validation stages
V1
100.00%
V2
92.86%
V2S
96.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 11.000s 75.186us 1 1 100.00
single_binary 1 1 100.00
otbn_single 18.000s 50.599us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 4.000s 97.103us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 5.000s 19.591us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 8.000s 132.133us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 4.000s 12.630us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 5.000s 41.233us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 5.000s 19.591us 1 1 100.00
otbn_csr_aliasing 4.000s 12.630us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 59.000s 5205.797us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 51.000s 20128.602us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 29.000s 116.035us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 46.000s 215.833us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 41.000s 545.727us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 107.000s 1654.946us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 8.000s 153.449us 1 1 100.00
zero_state_err_urnd 0 1 0.00
otbn_zero_state_err_urnd 5.000s 14.664us 0 1 0.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 6.000s 30.310us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 4.000s 43.019us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 3.000s 98.699us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 7.000s 315.533us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 7.000s 315.533us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 4.000s 97.103us 1 1 100.00
otbn_csr_rw 5.000s 19.591us 1 1 100.00
otbn_csr_aliasing 4.000s 12.630us 1 1 100.00
otbn_same_csr_outstanding 3.000s 77.987us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 4.000s 97.103us 1 1 100.00
otbn_csr_rw 5.000s 19.591us 1 1 100.00
otbn_csr_aliasing 4.000s 12.630us 1 1 100.00
otbn_same_csr_outstanding 3.000s 77.987us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 8.000s 48.579us 1 1 100.00
otbn_dmem_err 7.000s 27.450us 1 1 100.00
internal_integrity 4 4 100.00
otbn_alu_bignum_mod_err 8.000s 111.534us 1 1 100.00
otbn_controller_ispr_rdata_err 7.000s 21.391us 1 1 100.00
otbn_mac_bignum_acc_err 7.000s 44.279us 1 1 100.00
otbn_urnd_err 4.000s 10.299us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 7.000s 27.342us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 5.000s 12.787us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 6.000s 19.056us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 236.000s 4080.903us 1 1 100.00
otbn_tl_intg_err 17.000s 133.210us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 42.000s 396.331us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 236.000s 4080.903us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 236.000s 4080.903us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 11.000s 75.186us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 7.000s 27.450us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 8.000s 48.579us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 17.000s 133.210us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 8.000s 153.449us 1 1 100.00
sec_cm_controller_fsm_local_esc 4 5 80.00
otbn_imem_err 8.000s 48.579us 1 1 100.00
otbn_dmem_err 7.000s 27.450us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 14.664us 0 1 0.00
otbn_illegal_mem_acc 7.000s 27.342us 1 1 100.00
otbn_sec_cm 236.000s 4080.903us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 236.000s 4080.903us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 18.000s 50.599us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 8.000s 48.579us 1 1 100.00
otbn_dmem_err 7.000s 27.450us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 14.664us 0 1 0.00
otbn_illegal_mem_acc 7.000s 27.342us 1 1 100.00
otbn_sec_cm 236.000s 4080.903us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 236.000s 4080.903us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 8.000s 153.449us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 8.000s 48.579us 1 1 100.00
otbn_dmem_err 7.000s 27.450us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 14.664us 0 1 0.00
otbn_illegal_mem_acc 7.000s 27.342us 1 1 100.00
otbn_sec_cm 236.000s 4080.903us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 236.000s 4080.903us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 18.000s 50.599us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 6.000s 13.282us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 5.000s 22.846us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 18.000s 52.437us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 18.000s 52.437us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 8.000s 39.469us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 236.000s 4080.903us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 236.000s 4080.903us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 5.000s 171.475us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 236.000s 4080.903us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 236.000s 4080.903us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 11.000s 60.996us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 11.000s 60.996us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 5.000s 27.890us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 18.000s 50.599us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 18.000s 50.599us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 18.000s 50.599us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 41.000s 545.727us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 18.000s 50.599us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 18.000s 50.599us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 6.000s 50.369us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 18.000s 50.599us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 236.000s 4080.903us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 33.000s 535.821us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 6.000s 137.293us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
otbn_stress_all_with_rand_reset 5916606458931088554529948519065731782186239840262167227203993334480036449930 174
UVM_INFO @ 535821120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed 1 test run
otbn_zero_state_err_urnd 59919762694930308094265592692719802954332411321884645474607225529559825309226 110
UVM_ERROR @ 14663834 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 14663834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---