Simulation Results: otp_ctrl

 
22/05/2026 03:08:15 DVSim: v1.49.0 sha: d71121d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 70.84 %
  • code
  • 70.03 %
  • assert
  • 93.37 %
  • func
  • 49.12 %
  • line
  • 86.93 %
  • branch
  • 83.33 %
  • cond
  • 85.38 %
  • toggle
  • 61.95 %
  • FSM
  • 32.56 %
Validation stages
V1
100.00%
V2
55.00%
V2S
66.67%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.790s 108.534us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 6.060s 252.061us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.330s 329.078us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 2.170s 57.550us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 7.530s 4665.539us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 6.080s 979.444us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.130s 298.431us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 2.170s 57.550us 1 1 100.00
otp_ctrl_csr_aliasing 6.080s 979.444us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.430s 46.370us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.470s 154.632us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 106.070s 2404.337us 0 1 0.00
init_fail 0 1 0.00
otp_ctrl_init_fail 1.830s 90.845us 0 1 0.00
partition_check 1 2 50.00
otp_ctrl_background_chks 9.500s 1744.579us 0 1 0.00
otp_ctrl_check_fail 4.680s 359.424us 1 1 100.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 9.150s 5003.777us 1 1 100.00
partition_lock 0 1 0.00
otp_ctrl_dai_lock 3.160s 412.670us 0 1 0.00
interface_key_check 0 1 0.00
otp_ctrl_parallel_key_req 2.590s 980.534us 0 1 0.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 8.760s 618.716us 1 1 100.00
otp_ctrl_parallel_lc_esc 7.460s 854.797us 1 1 100.00
otp_dai_errors 0 1 0.00
otp_ctrl_dai_errs 6.270s 2587.823us 0 1 0.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 31.170s 19955.132us 0 1 0.00
test_access 0 1 0.00
otp_ctrl_test_access 3.900s 309.000us 0 1 0.00
stress_all 0 1 0.00
otp_ctrl_stress_all 13.280s 9239.719us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.450s 134.266us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 3.740s 1282.784us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 3.800s 131.447us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 3.800s 131.447us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.330s 329.078us 1 1 100.00
otp_ctrl_csr_rw 2.170s 57.550us 1 1 100.00
otp_ctrl_csr_aliasing 6.080s 979.444us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.320s 305.236us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.330s 329.078us 1 1 100.00
otp_ctrl_csr_rw 2.170s 57.550us 1 1 100.00
otp_ctrl_csr_aliasing 6.080s 979.444us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.320s 305.236us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 297.480s 21191.994us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 297.480s 21191.994us 1 1 100.00
otp_ctrl_tl_intg_err 24.360s 5112.459us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 297.480s 21191.994us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 297.480s 21191.994us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 24.360s 5112.459us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 6.060s 252.061us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 6.060s 252.061us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 297.480s 21191.994us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 297.480s 21191.994us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 297.480s 21191.994us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 297.480s 21191.994us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 297.480s 21191.994us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 297.480s 21191.994us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 297.480s 21191.994us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 297.480s 21191.994us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 297.480s 21191.994us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 297.480s 21191.994us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 297.480s 21191.994us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 297.480s 21191.994us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 297.480s 21191.994us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 297.480s 21191.994us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 297.480s 21191.994us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 7.460s 854.797us 1 1 100.00
otp_ctrl_sec_cm 297.480s 21191.994us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.460s 854.797us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.460s 854.797us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 7.460s 854.797us 1 1 100.00
otp_ctrl_macro_errs 31.170s 19955.132us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.460s 854.797us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 7.460s 854.797us 1 1 100.00
otp_ctrl_sec_cm 297.480s 21191.994us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 7.460s 854.797us 1 1 100.00
otp_ctrl_sec_cm 297.480s 21191.994us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.460s 854.797us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.460s 854.797us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 7.460s 854.797us 1 1 100.00
otp_ctrl_macro_errs 31.170s 19955.132us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.460s 854.797us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 7.460s 854.797us 1 1 100.00
otp_ctrl_sec_cm 297.480s 21191.994us 1 1 100.00
sec_cm_part_data_reg_integrity 0 1 0.00
otp_ctrl_init_fail 1.830s 90.845us 0 1 0.00
sec_cm_part_data_reg_bkgn_chk 1 1 100.00
otp_ctrl_check_fail 4.680s 359.424us 1 1 100.00
sec_cm_part_mem_regren 0 1 0.00
otp_ctrl_dai_lock 3.160s 412.670us 0 1 0.00
sec_cm_part_mem_sw_unreadable 0 1 0.00
otp_ctrl_dai_lock 3.160s 412.670us 0 1 0.00
sec_cm_part_mem_sw_unwritable 0 1 0.00
otp_ctrl_dai_lock 3.160s 412.670us 0 1 0.00
sec_cm_lc_part_mem_sw_noaccess 0 1 0.00
otp_ctrl_dai_lock 3.160s 412.670us 0 1 0.00
sec_cm_access_ctrl_mubi 0 1 0.00
otp_ctrl_dai_lock 3.160s 412.670us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 6.060s 252.061us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 0 1 0.00
otp_ctrl_dai_lock 3.160s 412.670us 0 1 0.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 6.060s 252.061us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 297.480s 21191.994us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 9.150s 5003.777us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 6.060s 252.061us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 6.060s 252.061us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 31.170s 19955.132us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 126.130s 64983.551us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 48.840s 24554.095us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_* 5 test runs
otp_ctrl_dai_lock 21003762584820495497298595736300525238378076191304885455681063336495604235213 1240
UVM_INFO @ 412669518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_errs 42061708488356423221651090810297993669344554576446951436907625204558726133716 1964
UVM_INFO @ 2587823247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_key_req 37339488809396699720870713932589943306752858768268683678697982231787229988046 704
UVM_INFO @ 980534040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_test_access 38449323461484115269186107076784545856536206898862576786156164593331872007696 1214
UVM_INFO @ 308999503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 79103711275806260815662931472361801969473440536535895046240863646447808728158 11448
UVM_INFO @ 9239719022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: * 2 test runs
otp_ctrl_partition_walk 72819505109316249411379126654529825747112986412973361281803352635215324653251 165303
UVM_INFO @ 2404336772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 80746974065256334473937261288364043987428626101709845780574204354201590765708 391
UVM_INFO @ 90845281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_low_freq_read 73507389549912224449950227610003595229942759738556435944929728449445952754100 89
UVM_INFO @ 64983550634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:958) [scoreboard] Check failed (csr.get_mirrored_value() | status_mask) == (item.d_data | status_mask) (* [*] vs * [*]) reg name: status, compare_mask * 1 test run
otp_ctrl_background_chks 55457513189061112173178951710624931547455630249509272174417897418640124304778 7143
UVM_INFO @ 1744579138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 1 test run
otp_ctrl_macro_errs 28984443305855457586374367826832005283647681797828635836814372546400184221068 13111
UVM_INFO @ 19955131987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 1 test run
otp_ctrl_stress_all_with_rand_reset 88758637754928257895860048323833152143573059388965119859819810088708070048731 3673
UVM_INFO @ 24554094556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---