Simulation Results: rom_ctrl/64kb

 
22/05/2026 03:08:15 DVSim: v1.49.0 sha: d71121d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.50 %
  • code
  • 94.37 %
  • assert
  • 96.79 %
  • func
  • 98.35 %
  • block
  • 96.32 %
  • line
  • 96.89 %
  • branch
  • 93.55 %
  • toggle
  • 87.03 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 5.000s 225.879us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 6.000s 389.330us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 5.000s 216.393us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 5.000s 1026.764us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 5.000s 394.388us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 5.000s 1105.800us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 5.000s 216.393us 1 1 100.00
rom_ctrl_csr_aliasing 5.000s 394.388us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 7.000s 2041.253us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 4.000s 650.062us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 5.000s 864.988us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 13.000s 596.198us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 9.000s 380.624us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 4.000s 1534.952us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 7.000s 318.413us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 7.000s 318.413us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 6.000s 389.330us 1 1 100.00
rom_ctrl_csr_rw 5.000s 216.393us 1 1 100.00
rom_ctrl_csr_aliasing 5.000s 394.388us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.000s 250.169us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 6.000s 389.330us 1 1 100.00
rom_ctrl_csr_rw 5.000s 216.393us 1 1 100.00
rom_ctrl_csr_aliasing 5.000s 394.388us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.000s 250.169us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 57.000s 4810.021us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 26.000s 6127.043us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 189.000s 2146.766us 1 1 100.00
rom_ctrl_tl_intg_err 47.000s 1253.476us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 189.000s 2146.766us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 189.000s 2146.766us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 57.000s 4810.021us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 57.000s 4810.021us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 57.000s 4810.021us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 57.000s 4810.021us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 57.000s 4810.021us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 189.000s 2146.766us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 189.000s 2146.766us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 5.000s 225.879us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 5.000s 225.879us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 5.000s 225.879us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 47.000s 1253.476us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 57.000s 4810.021us 1 1 100.00
rom_ctrl_kmac_err_chk 9.000s 380.624us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 57.000s 4810.021us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 57.000s 4810.021us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 57.000s 4810.021us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 26.000s 6127.043us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 189.000s 2146.766us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 122.000s 6791.482us 1 1 100.00