Simulation Results: rstmgr

 
22/05/2026 03:08:15 DVSim: v1.49.0 sha: d71121d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.41 %
  • code
  • 99.28 %
  • assert
  • 98.35 %
  • func
  • 97.59 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 98.41 %
  • toggle
  • 99.81 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.070s 56.102us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.110s 93.059us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 1.040s 37.255us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 2.320s 115.640us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.090s 43.893us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.210s 96.814us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 1.040s 37.255us 1 1 100.00
rstmgr_csr_aliasing 1.090s 43.893us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.340s 153.045us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.060s 44.265us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.010s 71.249us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 4.570s 617.445us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 4.570s 617.445us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 4.570s 617.445us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 4.570s 617.445us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 32.920s 5063.520us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.930s 37.973us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.150s 43.480us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.150s 43.480us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.110s 93.059us 1 1 100.00
rstmgr_csr_rw 1.040s 37.255us 1 1 100.00
rstmgr_csr_aliasing 1.090s 43.893us 1 1 100.00
rstmgr_same_csr_outstanding 1.020s 37.342us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.110s 93.059us 1 1 100.00
rstmgr_csr_rw 1.040s 37.255us 1 1 100.00
rstmgr_csr_aliasing 1.090s 43.893us 1 1 100.00
rstmgr_same_csr_outstanding 1.020s 37.342us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 30.660s 6752.904us 1 1 100.00
rstmgr_tl_intg_err 2.390s 332.089us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 30.660s 6752.904us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 30.660s 6752.904us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.390s 332.089us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.040s 67.503us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 3.480s 466.423us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.990s 292.422us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 30.660s 6752.904us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 1.040s 37.255us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 1.040s 37.255us 1 1 100.00