Simulation Results: rv_dm/use_dmi_interface

 
22/05/2026 03:08:15 DVSim: v1.49.0 sha: d71121d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 89.97 %
  • code
  • 82.78 %
  • assert
  • 96.74 %
  • func
  • 90.40 %
  • block
  • 92.52 %
  • line
  • 92.95 %
  • branch
  • 79.66 %
  • toggle
  • 78.15 %
  • FSM
  • 80.36 %
Validation stages
V1
96.30%
V2
73.91%
V2S
85.71%
V3
0.00%
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rv_dm_smoke 37.000s 2290.292us 1 1 100.00
jtag_dtm_csr_hw_reset 1 1 100.00
rv_dm_jtag_dtm_csr_hw_reset 30.000s 781.528us 1 1 100.00
jtag_dtm_csr_rw 1 1 100.00
rv_dm_jtag_dtm_csr_rw 31.000s 220.472us 1 1 100.00
jtag_dtm_csr_bit_bash 1 1 100.00
rv_dm_jtag_dtm_csr_bit_bash 37.000s 6619.937us 1 1 100.00
jtag_dtm_csr_aliasing 1 1 100.00
rv_dm_jtag_dtm_csr_aliasing 31.000s 999.738us 1 1 100.00
jtag_dmi_csr_hw_reset 1 1 100.00
rv_dm_jtag_dmi_csr_hw_reset 33.000s 2990.540us 1 1 100.00
jtag_dmi_csr_rw 1 1 100.00
rv_dm_jtag_dmi_csr_rw 37.000s 3116.146us 1 1 100.00
jtag_dmi_csr_bit_bash 1 1 100.00
rv_dm_jtag_dmi_csr_bit_bash 42.000s 26706.407us 1 1 100.00
jtag_dmi_csr_aliasing 1 1 100.00
rv_dm_jtag_dmi_csr_aliasing 45.000s 31857.466us 1 1 100.00
jtag_dmi_cmderr_busy 1 1 100.00
rv_dm_cmderr_busy 30.000s 283.409us 1 1 100.00
jtag_dmi_cmderr_not_supported 1 1 100.00
rv_dm_cmderr_not_supported 31.000s 182.214us 1 1 100.00
cmderr_exception 1 1 100.00
rv_dm_cmderr_exception 30.000s 397.429us 1 1 100.00
mem_tl_access_resuming 0 1 0.00
rv_dm_mem_tl_access_resuming 31.000s 172.262us 0 1 0.00
mem_tl_access_halted 1 1 100.00
rv_dm_mem_tl_access_halted 34.000s 180.429us 1 1 100.00
cmderr_halt_resume 1 1 100.00
rv_dm_cmderr_halt_resume 29.000s 176.503us 1 1 100.00
dataaddr_rw_access 1 1 100.00
rv_dm_dataaddr_rw_access 36.000s 182.485us 1 1 100.00
halt_resume 1 1 100.00
rv_dm_halt_resume_whereto 30.000s 340.976us 1 1 100.00
progbuf_busy 1 1 100.00
rv_dm_cmderr_busy 30.000s 283.409us 1 1 100.00
abstractcmd_status 1 1 100.00
rv_dm_abstractcmd_status 30.000s 109.961us 1 1 100.00
progbuf_read_write_execute 1 1 100.00
rv_dm_progbuf_read_write_execute 32.000s 280.574us 1 1 100.00
progbuf_exception 1 1 100.00
rv_dm_cmderr_exception 30.000s 397.429us 1 1 100.00
rom_read_access 1 1 100.00
rv_dm_rom_read_access 32.000s 179.597us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_dm_csr_hw_reset 31.000s 421.696us 1 1 100.00
csr_rw 1 1 100.00
rv_dm_csr_rw 32.000s 1231.507us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_dm_csr_bit_bash 72.000s 28748.388us 1 1 100.00
csr_aliasing 1 1 100.00
rv_dm_csr_aliasing 67.000s 8998.325us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_dm_csr_mem_rw_with_rand_reset 33.000s 219.700us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_dm_csr_aliasing 67.000s 8998.325us 1 1 100.00
rv_dm_csr_rw 32.000s 1231.507us 1 1 100.00
mem_walk 1 1 100.00
rv_dm_mem_walk 31.000s 36.597us 1 1 100.00
mem_partial_access 1 1 100.00
rv_dm_mem_partial_access 30.000s 53.399us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
idcode 1 1 100.00
rv_dm_smoke 37.000s 2290.292us 1 1 100.00
jtag_dtm_hard_reset 1 1 100.00
rv_dm_jtag_dtm_hard_reset 33.000s 572.624us 1 1 100.00
jtag_dtm_idle_hint 1 1 100.00
rv_dm_jtag_dtm_idle_hint 35.000s 520.981us 1 1 100.00
jtag_dmi_failed_op 1 1 100.00
rv_dm_dmi_failed_op 34.000s 693.135us 1 1 100.00
jtag_dmi_dm_inactive 1 1 100.00
rv_dm_jtag_dmi_dm_inactive 32.000s 1806.115us 1 1 100.00
sba 0 2 0.00
rv_dm_sba_tl_access 46.000s 7523.823us 0 1 0.00
rv_dm_delayed_resp_sba_tl_access 31.000s 231.382us 0 1 0.00
bad_sba 0 1 0.00
rv_dm_bad_sba_tl_access 32.000s 1252.873us 0 1 0.00
sba_autoincrement 1 1 100.00
rv_dm_autoincr_sba_tl_access 46.000s 12846.966us 1 1 100.00
jtag_dmi_debug_disabled 0 1 0.00
rv_dm_jtag_dmi_debug_disabled 31.000s 114.121us 0 1 0.00
sba_debug_disabled 1 1 100.00
rv_dm_sba_debug_disabled 32.000s 1039.912us 1 1 100.00
ndmreset_req 1 1 100.00
rv_dm_ndmreset_req 31.000s 320.012us 1 1 100.00
hart_unavail 0 1 0.00
rv_dm_hart_unavail 30.000s 51.824us 0 1 0.00
tap_ctrl_transitions 2 2 100.00
rv_dm_tap_fsm 39.000s 6024.306us 1 1 100.00
rv_dm_tap_fsm_rand_reset 37.000s 802.933us 1 1 100.00
hartsel_warl 1 1 100.00
rv_dm_hartsel_warl 32.000s 88.297us 1 1 100.00
stress_all 0 1 0.00
rv_dm_stress_all 31.000s 1354.204us 0 1 0.00
alert_test 1 1 100.00
rv_dm_alert_test 30.000s 133.130us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_dm_tl_errors 33.000s 1298.802us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_dm_tl_errors 33.000s 1298.802us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_dm_csr_aliasing 67.000s 8998.325us 1 1 100.00
rv_dm_csr_hw_reset 31.000s 421.696us 1 1 100.00
rv_dm_csr_rw 32.000s 1231.507us 1 1 100.00
rv_dm_same_csr_outstanding 35.000s 570.725us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_dm_csr_aliasing 67.000s 8998.325us 1 1 100.00
rv_dm_csr_hw_reset 31.000s 421.696us 1 1 100.00
rv_dm_csr_rw 32.000s 1231.507us 1 1 100.00
rv_dm_same_csr_outstanding 35.000s 570.725us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_dm_sec_cm 34.000s 696.522us 1 1 100.00
rv_dm_tl_intg_err 39.000s 1387.910us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_dm_tl_intg_err 39.000s 1387.910us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 2 50.00
rv_dm_sba_debug_disabled 32.000s 1039.912us 1 1 100.00
rv_dm_debug_disabled 34.000s 123.096us 0 1 0.00
sec_cm_lc_dft_en_intersig_mubi 1 2 50.00
rv_dm_sba_debug_disabled 32.000s 1039.912us 1 1 100.00
rv_dm_debug_disabled 34.000s 123.096us 0 1 0.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 1 1 100.00
rv_dm_smoke 37.000s 2290.292us 1 1 100.00
sec_cm_dm_en_ctrl_lc_gated 1 1 100.00
rv_dm_buffered_enable 30.000s 343.206us 1 1 100.00
sec_cm_sba_tl_lc_gate_fsm_sparse 1 1 100.00
rv_dm_sparse_lc_gate_fsm 31.000s 128.928us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
rv_dm_sparse_lc_gate_fsm 31.000s 128.928us 1 1 100.00
sec_cm_exec_ctrl_mubi 1 1 100.00
rv_dm_buffered_enable 30.000s 343.206us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
rv_dm_stress_all_with_rand_reset 59.000s 5697.491us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 1 0.00
rv_dm_scanmode 318.000s 300000.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (rv_dm_scoreboard.sv:414) [scoreboard] sba_tl_access_q item uncompared: 2 test runs
rv_dm_sba_tl_access 41047867696896145555495727000405742827675916166835586241299080179144701243757 87
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @10288
rv_dm_bad_sba_tl_access 47047550583832523972838828705318418969696582497477816918385105597534320131597 87
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @10288
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*]) 2 test runs
rv_dm_jtag_dmi_debug_disabled 10983709240617354592422956019848450415273215486230971393364505785409179638497 87
UVM_INFO @ 114120992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 11083595549183786921121631896318838611777989487820523498073627855156481072734 91
UVM_INFO @ 1354203982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (tl_device_seq.sv:151) sequencer [m_tl_sba_device_seq] Cannot randomize rsp 1 test run
rv_dm_delayed_resp_sba_tl_access 69289464170944783995432981883147496484018377733275042344842463885329574586787 107
UVM_INFO @ 231382203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == *'b* (* [*] vs * [*]) 1 test run
rv_dm_mem_tl_access_resuming 98806964319184148076627072129883246676645112407076365869779637724980234806627 87
UVM_INFO @ 172262195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [*] vs * [*]) 1 test run
rv_dm_hart_unavail 57799104033842983021611869079121790912597810354852903456491976308158260080113 87
UVM_INFO @ 51823931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_debug_disabled_vseq.sv:33) [rv_dm_debug_disabled_vseq] Check failed (rvalue == expected_output) 1 test run
rv_dm_debug_disabled 89142686142216319745713939051255618606267715970935003350572933794893790054993 90
UVM_INFO @ 123096425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
rv_dm_scanmode 99129284953463666003111186410504447895884293464060512133513934510244739353916 87
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [rv_dm_common_vseq] Check failed (vseq_done) 1 test run
rv_dm_stress_all_with_rand_reset 89518310404618081727791971180588837746810676519889842681198770322691329686261 163
UVM_INFO @ 5697491418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---