Simulation Results: spi_device/1r1w

 
22/05/2026 03:08:15 DVSim: v1.49.0 sha: d71121d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 84.95 %
  • code
  • 91.61 %
  • assert
  • 95.39 %
  • func
  • 67.84 %
  • block
  • 98.30 %
  • line
  • 98.68 %
  • branch
  • 96.91 %
  • toggle
  • 81.25 %
  • FSM
  • 89.58 %
Validation stages
V1
100.00%
V2
92.31%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 132.000s 54791.677us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.000s 75.293us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 3.000s 72.327us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 15.000s 1268.610us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 9.000s 393.229us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.000s 23.930us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 3.000s 72.327us 1 1 100.00
spi_device_csr_aliasing 9.000s 393.229us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 2.000s 16.750us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 2.000s 256.958us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 2.000s 16.758us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 2.000s 2.831us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 1.000s 3.544us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 2.000s 13.585us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 2.000s 13.585us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 5.000s 313.309us 1 1 100.00
spi_device_tpm_sts_read 2.000s 52.845us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 21.000s 943.486us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 48.000s 7706.173us 1 1 100.00
spi_device_flash_all 141.000s 15979.941us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 7.000s 2102.363us 1 1 100.00
spi_device_flash_all 141.000s 15979.941us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 7.000s 2102.363us 1 1 100.00
spi_device_flash_all 141.000s 15979.941us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 141.000s 15979.941us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 5.000s 221.137us 1 1 100.00
spi_device_flash_all 141.000s 15979.941us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 5.000s 221.137us 1 1 100.00
spi_device_flash_all 141.000s 15979.941us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 5.000s 221.137us 1 1 100.00
spi_device_flash_all 141.000s 15979.941us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 5.000s 221.137us 1 1 100.00
spi_device_flash_all 141.000s 15979.941us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 5.000s 221.137us 1 1 100.00
spi_device_flash_all 141.000s 15979.941us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 12.000s 5558.900us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 11.000s 14479.182us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 11.000s 14479.182us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 11.000s 14479.182us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 14.000s 2326.830us 1 1 100.00
spi_device_read_buffer_direct 8.000s 244.434us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 11.000s 14479.182us 1 1 100.00
spi_device_flash_all 141.000s 15979.941us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 141.000s 15979.941us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 141.000s 15979.941us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 4.000s 1520.931us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 4.000s 1520.931us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 132.000s 54791.677us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 95.000s 4838.615us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 90.000s 21849.296us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 2.000s 12.409us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 1.000s 196.269us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 5.000s 738.431us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 5.000s 738.431us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.000s 75.293us 1 1 100.00
spi_device_csr_rw 3.000s 72.327us 1 1 100.00
spi_device_csr_aliasing 9.000s 393.229us 1 1 100.00
spi_device_same_csr_outstanding 3.000s 60.754us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.000s 75.293us 1 1 100.00
spi_device_csr_rw 3.000s 72.327us 1 1 100.00
spi_device_csr_aliasing 9.000s 393.229us 1 1 100.00
spi_device_same_csr_outstanding 3.000s 60.754us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 2.000s 74.187us 1 1 100.00
spi_device_tl_intg_err 7.000s 1341.644us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 7.000s 1341.644us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 99.000s 12694.599us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ1] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice) 1 test run
spi_device_mem_parity 64318268059093130775568302256456091826741832343712350459561001921878978089586 87
UVM_ERROR @ 2277327 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
ERROR: VHPI NOTFOUND
Name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[947] not found within the scope .
UVM_ERROR @ 2277327 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ2] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[947] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 108884319083251717099463725130443477205988304871140983145105566466723068962122 85
UVM_ERROR @ 1144277 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3a9560 [1110101001010101100000] vs 0x0 [0])
UVM_ERROR @ 1169277 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xe25b94 [111000100101101110010100] vs 0x0 [0])
UVM_ERROR @ 1251277 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x6afa70 [11010101111101001110000] vs 0x0 [0])
UVM_ERROR @ 1316277 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x5bc5c9 [10110111100010111001001] vs 0x0 [0])