Simulation Results: spi_host

 
22/05/2026 03:08:15 DVSim: v1.49.0 sha: d71121d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.19 %
  • code
  • 94.98 %
  • assert
  • 96.78 %
  • func
  • 87.82 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 87.81 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 29.000s 4419.089us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 37.036us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 2.000s 20.821us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 2.000s 59.181us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 58.344us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 26.169us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 2.000s 20.821us 1 1 100.00
spi_host_csr_aliasing 1.000s 58.344us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 17.969us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 128.064us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 1.000s 24.841us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 2.000s 216.120us 1 1 100.00
spi_host_error_cmd 2.000s 65.198us 1 1 100.00
spi_host_event 10.000s 1542.578us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 3.000s 234.840us 1 1 100.00
speed 1 1 100.00
spi_host_speed 3.000s 234.840us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 3.000s 234.840us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 1.000s 50.090us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 52.023us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 3.000s 234.840us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 3.000s 234.840us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 29.000s 4419.089us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 29.000s 4419.089us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 5.000s 283.442us 1 1 100.00
spien 1 1 100.00
spi_host_spien 7.000s 1682.958us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 50.000s 15202.352us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 2.000s 86.632us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 2.000s 216.120us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 1.000s 18.235us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 27.635us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 2.000s 180.834us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 2.000s 180.834us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 37.036us 1 1 100.00
spi_host_csr_rw 2.000s 20.821us 1 1 100.00
spi_host_csr_aliasing 1.000s 58.344us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 66.628us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 37.036us 1 1 100.00
spi_host_csr_rw 2.000s 20.821us 1 1 100.00
spi_host_csr_aliasing 1.000s 58.344us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 66.628us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 1.000s 535.194us 1 1 100.00
spi_host_sec_cm 1.000s 51.303us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 1.000s 535.194us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_host_upper_range_clkdiv 236.000s 12367.401us 1 1 100.00