Simulation Results: sram_ctrl/main

 
22/05/2026 03:08:15 DVSim: v1.49.0 sha: d71121d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.54 %
  • code
  • 96.78 %
  • assert
  • 97.82 %
  • func
  • 92.00 %
  • block
  • 96.08 %
  • line
  • 96.88 %
  • branch
  • 94.17 %
  • toggle
  • 96.09 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 3.000s 371.436us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 20.146us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 25.647us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 209.736us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 47.539us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 1118.892us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 25.647us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 47.539us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 180.000s 10103.839us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 49.000s 3059.139us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 28.000s 7015.565us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 97.000s 15634.779us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 147.000s 13856.309us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 44.000s 26933.784us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 17.000s 4886.427us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 20.000s 5110.321us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 1396.260us 1 1 100.00
sram_ctrl_partial_access_b2b 123.000s 3673.720us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 3.000s 2803.594us 1 1 100.00
sram_ctrl_throughput_w_partial_write 5.000s 3037.504us 1 1 100.00
sram_ctrl_throughput_w_readback 4.000s 674.423us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 9.000s 1115.572us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 1025.434us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 218.000s 124920.434us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 15.389us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 123.146us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 123.146us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 20.146us 1 1 100.00
sram_ctrl_csr_rw 1.000s 25.647us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 47.539us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 19.757us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 20.146us 1 1 100.00
sram_ctrl_csr_rw 1.000s 25.647us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 47.539us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 19.757us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 13.000s 3911.181us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 4.000s 611.484us 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 301.764us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 4.000s 611.484us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 301.764us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 9.000s 1115.572us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 9.000s 1115.572us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 25.647us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 20.000s 5110.321us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 20.000s 5110.321us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 20.000s 5110.321us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 17.000s 4886.427us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 4.000s 9641.686us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 13.000s 3911.181us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 4.000s 667.681us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 371.436us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 371.436us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 20.000s 5110.321us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 4.000s 611.484us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 17.000s 4886.427us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 4.000s 611.484us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 611.484us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 3.000s 371.436us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 611.484us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 12.000s 1978.651us 1 1 100.00