Simulation Results: sram_ctrl/ret

 
22/05/2026 03:08:15 DVSim: v1.49.0 sha: d71121d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.37 %
  • code
  • 83.06 %
  • assert
  • 97.25 %
  • func
  • 93.80 %
  • block
  • 93.46 %
  • line
  • 94.59 %
  • branch
  • 88.89 %
  • toggle
  • 82.08 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 1.000s 78.965us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 54.329us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 49.537us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 154.220us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 113.079us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 51.062us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 49.537us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 113.079us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 5.000s 4600.866us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 5.000s 330.705us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 4.000s 544.286us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 117.000s 2462.720us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 6.000s 539.138us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 12.000s 565.475us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 2.000s 720.703us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 3.000s 471.250us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 1.000s 81.746us 1 1 100.00
sram_ctrl_partial_access_b2b 141.000s 4129.535us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 1.000s 127.266us 1 1 100.00
sram_ctrl_throughput_w_partial_write 2.000s 185.016us 1 1 100.00
sram_ctrl_throughput_w_readback 2.000s 43.013us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 6.000s 1798.584us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 1.000s 44.465us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 21.000s 9158.428us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 11.188us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 129.555us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 129.555us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 54.329us 1 1 100.00
sram_ctrl_csr_rw 1.000s 49.537us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 113.079us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 71.256us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 54.329us 1 1 100.00
sram_ctrl_csr_rw 1.000s 49.537us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 113.079us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 71.256us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 4.000s 455.965us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 687.304us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 213.240us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 687.304us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 213.240us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 6.000s 1798.584us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 6.000s 1798.584us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 49.537us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 3.000s 471.250us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 3.000s 471.250us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 3.000s 471.250us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 2.000s 720.703us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 2.000s 69.031us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 4.000s 455.965us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 2.000s 33.743us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 1.000s 78.965us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 1.000s 78.965us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 3.000s 471.250us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 687.304us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 2.000s 720.703us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 687.304us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 687.304us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 1.000s 78.965us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 687.304us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 50.000s 7432.334us 1 1 100.00