Simulation Results: uart

 
22/05/2026 03:08:15 DVSim: v1.49.0 sha: d71121d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.82 %
  • code
  • 96.65 %
  • assert
  • 97.12 %
  • func
  • 90.69 %
  • block
  • 99.08 %
  • line
  • 99.52 %
  • branch
  • 98.34 %
  • toggle
  • 88.74 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 17.000s 5892.252us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 1.000s 13.019us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 1.000s 66.156us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 2.000s 456.728us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 1.000s 212.714us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 1.000s 56.459us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 1.000s 66.156us 1 1 100.00
uart_csr_aliasing 1.000s 212.714us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 72.000s 92492.688us 1 1 100.00
parity 2 2 100.00
uart_smoke 17.000s 5892.252us 1 1 100.00
uart_tx_rx 72.000s 92492.688us 1 1 100.00
parity_error 2 2 100.00
uart_intr 174.000s 120126.262us 1 1 100.00
uart_rx_parity_err 15.000s 31417.734us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 72.000s 92492.688us 1 1 100.00
uart_intr 174.000s 120126.262us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 59.000s 154406.107us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 150.000s 95517.760us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 11.000s 7611.532us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 174.000s 120126.262us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 174.000s 120126.262us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 174.000s 120126.262us 1 1 100.00
perf 1 1 100.00
uart_perf 69.000s 12005.015us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 17.000s 11313.170us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 17.000s 11313.170us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 4.000s 1204.876us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 4.000s 6133.647us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 13.000s 7015.473us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 9.000s 4533.599us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 197.000s 93408.949us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 11.000s 66756.520us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 1.000s 35.203us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 1.000s 111.448us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.000s 74.857us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.000s 74.857us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 1.000s 13.019us 1 1 100.00
uart_csr_rw 1.000s 66.156us 1 1 100.00
uart_csr_aliasing 1.000s 212.714us 1 1 100.00
uart_same_csr_outstanding 1.000s 18.392us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 1.000s 13.019us 1 1 100.00
uart_csr_rw 1.000s 66.156us 1 1 100.00
uart_csr_aliasing 1.000s 212.714us 1 1 100.00
uart_same_csr_outstanding 1.000s 18.392us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 1.000s 39.292us 1 1 100.00
uart_tl_intg_err 1.000s 367.384us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.000s 367.384us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 17.000s 5716.855us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:395) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * 1 test run
uart_noise_filter 42436946682350410007878240521472279162083748037620991857804878124332835538028 83
UVM_ERROR @ 22426004 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 100706004 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 101876004 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 119926004 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (228 [0xe4] vs 35 [0x23]) reg name: uart_reg_block.rdata