Simulation Results: ac_range_check

 
25/05/2026 19:40:27 DVSim: v1.49.1 sha: f988e3e json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 82.93 %
  • code
  • 93.15 %
  • assert
  • 97.75 %
  • func
  • 57.88 %
  • block
  • 99.10 %
  • line
  • 99.93 %
  • branch
  • 98.24 %
  • toggle
  • 81.27 %
Validation stages
V1
100.00%
V2
90.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 1 1 100.00
ac_range_check_smoke 28.000s 1341.932us 1 1 100.00
ac_range_check_smoke_racl 1 1 100.00
ac_range_check_smoke_racl 50.000s 4999.768us 1 1 100.00
csr_hw_reset 1 1 100.00
ac_range_check_csr_hw_reset 2.000s 264.738us 1 1 100.00
csr_rw 1 1 100.00
ac_range_check_csr_rw 3.000s 101.982us 1 1 100.00
csr_bit_bash 1 1 100.00
ac_range_check_csr_bit_bash 21.000s 507.515us 1 1 100.00
csr_aliasing 1 1 100.00
ac_range_check_csr_aliasing 16.000s 1438.192us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
ac_range_check_csr_mem_rw_with_rand_reset 2.000s 156.687us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
ac_range_check_csr_rw 3.000s 101.982us 1 1 100.00
ac_range_check_csr_aliasing 16.000s 1438.192us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 1 1 100.00
ac_range_check_lock_range 3.000s 58.096us 1 1 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 30.000s 1655.757us 1 1 100.00
stress_all 0 1 0.00
ac_range_check_stress_all 39.000s 7807.196us 0 1 0.00
alert_test 1 1 100.00
ac_range_check_alert_test 1.000s 117.599us 1 1 100.00
intr_test 1 1 100.00
ac_range_check_intr_test 2.000s 13.020us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
ac_range_check_tl_errors 2.000s 127.573us 1 1 100.00
tl_d_illegal_access 1 1 100.00
ac_range_check_tl_errors 2.000s 127.573us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
ac_range_check_csr_hw_reset 2.000s 264.738us 1 1 100.00
ac_range_check_csr_rw 3.000s 101.982us 1 1 100.00
ac_range_check_csr_aliasing 16.000s 1438.192us 1 1 100.00
ac_range_check_same_csr_outstanding 4.000s 167.718us 1 1 100.00
tl_d_partial_access 4 4 100.00
ac_range_check_csr_hw_reset 2.000s 264.738us 1 1 100.00
ac_range_check_csr_rw 3.000s 101.982us 1 1 100.00
ac_range_check_csr_aliasing 16.000s 1438.192us 1 1 100.00
ac_range_check_same_csr_outstanding 4.000s 167.718us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
ac_range_check_shadow_reg_errors 15.000s 1086.440us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
ac_range_check_shadow_reg_errors 15.000s 1086.440us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
ac_range_check_shadow_reg_errors 15.000s 1086.440us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
ac_range_check_shadow_reg_errors 15.000s 1086.440us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 79.000s 8503.522us 1 1 100.00
tl_intg_err 2 2 100.00
ac_range_check_sec_cm 1.000s 91.449us 1 1 100.00
ac_range_check_tl_intg_err 7.000s 682.946us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
ac_range_check_stress_all_with_rand_reset 271.000s 7457.964us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
ac_range_check_smoke_high_threshold 28.000s 10058.615us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (ac_range_check_scoreboard.sv:374) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: ac_range_check_reg_block.intr_state 1 test run
ac_range_check_stress_all 87957285596435345489586438585079494569566523313315147020892535859107451805787 4169
UVM_INFO @ 7807196142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---