Simulation Results: aes/gcm_unmasked

 
25/05/2026 19:40:27 DVSim: v1.49.1 sha: f988e3e json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 84.21 %
  • code
  • 90.86 %
  • assert
  • 97.75 %
  • func
  • 64.02 %
  • block
  • 91.12 %
  • line
  • 93.02 %
  • branch
  • 83.78 %
  • toggle
  • 97.99 %
  • FSM
  • 88.65 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 60.342us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 171.232us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 65.383us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 78.034us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 3.000s 336.243us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 121.347us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 74.027us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 78.034us 1 1 100.00
aes_csr_aliasing 2.000s 121.347us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 171.232us 1 1 100.00
aes_config_error 3.000s 336.117us 1 1 100.00
aes_stress 2.000s 68.935us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 171.232us 1 1 100.00
aes_config_error 3.000s 336.117us 1 1 100.00
aes_stress 2.000s 68.935us 1 1 100.00
back2back 2 2 100.00
aes_stress 2.000s 68.935us 1 1 100.00
aes_b2b 3.000s 166.494us 1 1 100.00
backpressure 1 1 100.00
aes_stress 2.000s 68.935us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 171.232us 1 1 100.00
aes_config_error 3.000s 336.117us 1 1 100.00
aes_stress 2.000s 68.935us 1 1 100.00
aes_alert_reset 2.000s 256.548us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 127.115us 1 1 100.00
aes_config_error 3.000s 336.117us 1 1 100.00
aes_alert_reset 2.000s 256.548us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 7.000s 165.777us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 5.000s 151.620us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 2.000s 256.548us 1 1 100.00
stress 1 1 100.00
aes_stress 2.000s 68.935us 1 1 100.00
sideload 2 2 100.00
aes_stress 2.000s 68.935us 1 1 100.00
aes_sideload 2.000s 219.072us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 85.032us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 2.000s 597.976us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 65.836us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 133.483us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 133.483us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 65.383us 1 1 100.00
aes_csr_rw 2.000s 78.034us 1 1 100.00
aes_csr_aliasing 2.000s 121.347us 1 1 100.00
aes_same_csr_outstanding 2.000s 419.458us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 65.383us 1 1 100.00
aes_csr_rw 2.000s 78.034us 1 1 100.00
aes_csr_aliasing 2.000s 121.347us 1 1 100.00
aes_same_csr_outstanding 2.000s 419.458us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 2.000s 130.787us 1 1 100.00
fault_inject 3 3 100.00
aes_fi 3.000s 67.308us 1 1 100.00
aes_control_fi 2.000s 48.109us 1 1 100.00
aes_cipher_fi 3.000s 337.294us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 155.803us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 155.803us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 155.803us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 155.803us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 4.000s 568.776us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 5.000s 1006.961us 1 1 100.00
aes_tl_intg_err 2.000s 327.684us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 327.684us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 2.000s 256.548us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 155.803us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 155.803us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 2.000s 171.232us 1 1 100.00
aes_stress 2.000s 68.935us 1 1 100.00
aes_alert_reset 2.000s 256.548us 1 1 100.00
aes_core_fi 2.000s 105.022us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 3.000s 336.117us 1 1 100.00
aes_stress 2.000s 68.935us 1 1 100.00
aes_core_fi 2.000s 105.022us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 155.803us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 1.000s 78.296us 1 1 100.00
aes_stress 2.000s 68.935us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 2.000s 68.935us 1 1 100.00
aes_sideload 2.000s 219.072us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 1.000s 78.296us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 1.000s 78.296us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 1.000s 78.296us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 1.000s 78.296us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 1.000s 78.296us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 2.000s 68.935us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 2.000s 68.935us 1 1 100.00
sec_cm_main_fsm_sparse 1 1 100.00
aes_fi 3.000s 67.308us 1 1 100.00
sec_cm_main_fsm_redun 4 4 100.00
aes_fi 3.000s 67.308us 1 1 100.00
aes_control_fi 2.000s 48.109us 1 1 100.00
aes_cipher_fi 3.000s 337.294us 1 1 100.00
aes_ctr_fi 2.000s 75.976us 1 1 100.00
sec_cm_cipher_fsm_sparse 1 1 100.00
aes_fi 3.000s 67.308us 1 1 100.00
sec_cm_cipher_fsm_redun 3 3 100.00
aes_fi 3.000s 67.308us 1 1 100.00
aes_control_fi 2.000s 48.109us 1 1 100.00
aes_cipher_fi 3.000s 337.294us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 3.000s 337.294us 1 1 100.00
sec_cm_ctr_fsm_sparse 1 1 100.00
aes_fi 3.000s 67.308us 1 1 100.00
sec_cm_ctr_fsm_redun 3 3 100.00
aes_fi 3.000s 67.308us 1 1 100.00
aes_control_fi 2.000s 48.109us 1 1 100.00
aes_ctr_fi 2.000s 75.976us 1 1 100.00
sec_cm_ghash_fsm_sparse 1 1 100.00
aes_fi 3.000s 67.308us 1 1 100.00
sec_cm_ctrl_sparse 4 4 100.00
aes_fi 3.000s 67.308us 1 1 100.00
aes_control_fi 2.000s 48.109us 1 1 100.00
aes_cipher_fi 3.000s 337.294us 1 1 100.00
aes_ctr_fi 2.000s 75.976us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 2.000s 256.548us 1 1 100.00
sec_cm_main_fsm_local_esc 4 4 100.00
aes_fi 3.000s 67.308us 1 1 100.00
aes_control_fi 2.000s 48.109us 1 1 100.00
aes_cipher_fi 3.000s 337.294us 1 1 100.00
aes_ctr_fi 2.000s 75.976us 1 1 100.00
sec_cm_cipher_fsm_local_esc 4 4 100.00
aes_fi 3.000s 67.308us 1 1 100.00
aes_control_fi 2.000s 48.109us 1 1 100.00
aes_cipher_fi 3.000s 337.294us 1 1 100.00
aes_ctr_fi 2.000s 75.976us 1 1 100.00
sec_cm_ctr_fsm_local_esc 3 3 100.00
aes_fi 3.000s 67.308us 1 1 100.00
aes_control_fi 2.000s 48.109us 1 1 100.00
aes_ctr_fi 2.000s 75.976us 1 1 100.00
sec_cm_ghash_fsm_local_esc 1 1 100.00
aes_fi 3.000s 67.308us 1 1 100.00
sec_cm_data_reg_local_esc 3 3 100.00
aes_fi 3.000s 67.308us 1 1 100.00
aes_control_fi 2.000s 48.109us 1 1 100.00
aes_cipher_fi 3.000s 337.294us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 21.000s 2543.971us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
aes_stress_all_with_rand_reset 23934740684574278670417278594379179489863788002885053171070414471113781499814 992
UVM_INFO @ 2543971402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---