Simulation Results: alert_handler

 
25/05/2026 19:40:27 DVSim: v1.49.1 sha: f988e3e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.93 %
  • code
  • 90.87 %
  • assert
  • 98.20 %
  • func
  • 74.72 %
  • line
  • 99.70 %
  • branch
  • 98.18 %
  • cond
  • 92.17 %
  • toggle
  • 85.29 %
  • FSM
  • 79.03 %
Validation stages
V1
100.00%
V2
84.21%
V2S
87.50%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 16.120s 242.220us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 8.220s 522.656us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 4.930s 753.708us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 206.950s 5954.350us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 104.400s 1309.554us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 5.630s 290.344us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 4.930s 753.708us 1 1 100.00
alert_handler_csr_aliasing 104.400s 1309.554us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 25.620s 584.658us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 48.090s 4649.157us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 1206.360s 20107.820us 1 1 100.00
sig_int_fail 0 1 0.00
alert_handler_sig_int_fail 10.030s 397.251us 0 1 0.00
clk_skew 1 1 100.00
alert_handler_smoke 16.120s 242.220us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 43.840s 3896.286us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 38.680s 1251.279us 1 1 100.00
ping_timeout 0 1 0.00
alert_handler_ping_timeout 19.390s 2399.608us 0 1 0.00
lpg 2 2 100.00
alert_handler_lpg 2320.160s 115496.830us 1 1 100.00
alert_handler_lpg_stub_clk 2658.620s 95083.128us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 71.060s 5115.036us 1 1 100.00
alert_handler_entropy_stress_test 0 1 0.00
alert_handler_entropy_stress 5.630s 384.654us 0 1 0.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 3.760s 119.480us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.400s 9.298us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 9.760s 189.702us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 9.760s 189.702us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 8.220s 522.656us 1 1 100.00
alert_handler_csr_rw 4.930s 753.708us 1 1 100.00
alert_handler_csr_aliasing 104.400s 1309.554us 1 1 100.00
alert_handler_same_csr_outstanding 9.020s 429.727us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 8.220s 522.656us 1 1 100.00
alert_handler_csr_rw 4.930s 753.708us 1 1 100.00
alert_handler_csr_aliasing 104.400s 1309.554us 1 1 100.00
alert_handler_same_csr_outstanding 9.020s 429.727us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 256.360s 5417.292us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 256.360s 5417.292us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 256.360s 5417.292us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 256.360s 5417.292us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 445.600s 9571.348us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 12.200s 892.224us 1 1 100.00
alert_handler_tl_intg_err 3.910s 231.858us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 3.910s 231.858us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 256.360s 5417.292us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 16.120s 242.220us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 16.120s 242.220us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 16.120s 242.220us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 16.120s 242.220us 1 1 100.00
sec_cm_alert_intersig_diff 0 1 0.00
alert_handler_sig_int_fail 10.030s 397.251us 0 1 0.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 2320.160s 115496.830us 1 1 100.00
sec_cm_esc_intersig_diff 0 1 0.00
alert_handler_sig_int_fail 10.030s 397.251us 0 1 0.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1206.360s 20107.820us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1206.360s 20107.820us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 12.200s 892.224us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 12.200s 892.224us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 12.200s 892.224us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 12.200s 892.224us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 12.200s 892.224us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 12.200s 892.224us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 12.200s 892.224us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 12.200s 892.224us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 12.200s 892.224us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
alert_handler_stress_all_with_rand_reset 152.690s 7378.379us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:258) scoreboard [scoreboard] Unexpected interrupt value in cfg.intr_vif.pins[*]: saw *, but expected *. (is_int_err = *, local_alert_type = LocalEscIntFail) 1 test run
alert_handler_sig_int_fail 72134719079733058055663301029750191747403234077787850573919542584883233158105 82
UVM_INFO @ 397250905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_handler_scoreboard.sv:608) scoreboard [scoreboard] Register/crashdump mismatch. loc_alert_cause[*] is * in the crashdump and * in the register model. 1 test run
alert_handler_ping_timeout 88498572271136923399398371828815745150343119032900773301123978375843579885130 80
UVM_INFO @ 2399607784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped 1 test run
alert_handler_entropy_stress 108025356755184431881064769681029481226117911721944473755671973585713120552671 200
UVM_INFO @ 384654071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---