Simulation Results: clkmgr

 
25/05/2026 19:40:27 DVSim: v1.49.1 sha: f988e3e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 73.75 %
  • code
  • 67.25 %
  • assert
  • 87.60 %
  • func
  • 66.40 %
  • line
  • 81.10 %
  • branch
  • 85.86 %
  • cond
  • 74.46 %
  • toggle
  • 94.81 %
  • FSM
  • 0.00 %
Validation stages
V1
83.33%
V2
69.23%
V2S
25.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.160s 23.472us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.900s 28.895us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.950s 44.647us 1 1 100.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 0.730s 3.898us 0 1 0.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.480s 61.353us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.740s 59.621us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.950s 44.647us 1 1 100.00
clkmgr_csr_aliasing 1.480s 61.353us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.770s 16.985us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.190s 33.188us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 1.010s 46.352us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.160s 23.472us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.900s 9.300us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.740s 6.511us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.900s 9.300us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 0.920s 36.120us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 0.830s 14.067us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.700s 27.747us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.700s 27.747us 1 1 100.00
tl_d_outstanding_access 3 4 75.00
clkmgr_csr_hw_reset 0.900s 28.895us 1 1 100.00
clkmgr_csr_rw 0.950s 44.647us 1 1 100.00
clkmgr_csr_aliasing 1.480s 61.353us 1 1 100.00
clkmgr_same_csr_outstanding 0.850s 9.237us 0 1 0.00
tl_d_partial_access 3 4 75.00
clkmgr_csr_hw_reset 0.900s 28.895us 1 1 100.00
clkmgr_csr_rw 0.950s 44.647us 1 1 100.00
clkmgr_csr_aliasing 1.480s 61.353us 1 1 100.00
clkmgr_same_csr_outstanding 0.850s 9.237us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
clkmgr_sec_cm 89.760s 10031.488us 0 1 0.00
clkmgr_tl_intg_err 0.790s 6.738us 0 1 0.00
shadow_reg_update_error 0 1 0.00
clkmgr_shadow_reg_errors 1862.860s 200000.000us 0 1 0.00
shadow_reg_read_clear_staged_value 0 1 0.00
clkmgr_shadow_reg_errors 1862.860s 200000.000us 0 1 0.00
shadow_reg_storage_error 0 1 0.00
clkmgr_shadow_reg_errors 1862.860s 200000.000us 0 1 0.00
shadowed_reset_glitch 0 1 0.00
clkmgr_shadow_reg_errors 1862.860s 200000.000us 0 1 0.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.710s 5.053us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 0.790s 6.738us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.900s 9.300us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.740s 6.511us 0 1 0.00
sec_cm_meas_config_shadow 0 1 0.00
clkmgr_shadow_reg_errors 1862.860s 200000.000us 0 1 0.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.930s 27.991us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.950s 44.647us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 89.760s 10031.488us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.950s 44.647us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.950s 44.647us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 89.760s 10031.488us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.620s 2.828us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 15.520s 1547.681us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* 2 test runs
clkmgr_frequency 10681868663053410096598461837968445371141774737350319691186601470215003019331 78
UVM_INFO @ 9299756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 111812644052076733278705603036118638429049580263586384079360590482131593011468 76
UVM_INFO @ 36119607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b* 2 test runs
clkmgr_frequency_timeout 107823506060605921135904372583474389390784252332686482392353600629349849124982 78
UVM_INFO @ 6510946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 97631037789399453558093696900680243153886018104278649713456906873223568390514 213
UVM_INFO @ 1547681233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed 1 test run
clkmgr_regwen 59006569939221646730579201012636843594344321812242364496519857126886150031098 74
UVM_INFO @ 2827601 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
clkmgr_shadow_reg_errors 82836282927951232733154265005935161856723901436918732129264451059860671784197 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: * 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 113230418932382912248288587730562917916230663780655872404113236847124863297934 75
UVM_INFO @ 5053058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1077) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault 1 test run
clkmgr_sec_cm 66506265095150013759146510412278870337159265300994502322045021118444653582487 96
UVM_INFO @ 10031487692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * 1 test run
clkmgr_tl_intg_err 9126189252315431288257865444461063680416517173806124720066731268516263665217 85
UVM_INFO @ 6738336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: * 1 test run
clkmgr_csr_bit_bash 80132186994586737278464052633200286634563724977825828349052082606198647892150 75
UVM_INFO @ 3898094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:660) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
clkmgr_same_csr_outstanding 74743942590782797633955339339040283436750833551358711121087407990394422591883 75
UVM_INFO @ 9236605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---