Simulation Results: csrng

 
25/05/2026 19:40:27 DVSim: v1.49.1 sha: f988e3e json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.88 %
  • code
  • 92.25 %
  • assert
  • 93.89 %
  • func
  • 77.49 %
  • block
  • 96.89 %
  • line
  • 97.66 %
  • branch
  • 92.26 %
  • toggle
  • 93.37 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
91.67%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 2.000s 17.432us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 1.000s 14.926us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 2.000s 18.634us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 7.000s 173.697us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 3.000s 47.832us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 2.000s 21.885us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 2.000s 18.634us 1 1 100.00
csrng_csr_aliasing 3.000s 47.832us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 4.000s 71.692us 1 1 100.00
alerts 1 1 100.00
csrng_alert 7.000s 282.325us 1 1 100.00
err 1 1 100.00
csrng_err 1.000s 20.653us 1 1 100.00
cmds 0 1 0.00
csrng_cmds 2.000s 8.101us 0 1 0.00
life cycle 0 1 0.00
csrng_cmds 2.000s 8.101us 0 1 0.00
stress_all 1 1 100.00
csrng_stress_all 178.000s 5611.178us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 2.000s 48.904us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 3.000s 233.114us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 6.000s 126.417us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 6.000s 126.417us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 1.000s 14.926us 1 1 100.00
csrng_csr_rw 2.000s 18.634us 1 1 100.00
csrng_csr_aliasing 3.000s 47.832us 1 1 100.00
csrng_same_csr_outstanding 2.000s 18.105us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 1.000s 14.926us 1 1 100.00
csrng_csr_rw 2.000s 18.634us 1 1 100.00
csrng_csr_aliasing 3.000s 47.832us 1 1 100.00
csrng_same_csr_outstanding 2.000s 18.105us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 3.000s 133.630us 1 1 100.00
csrng_tl_intg_err 6.000s 231.482us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
csrng_regwen 2.000s 29.628us 1 1 100.00
csrng_csr_rw 2.000s 18.634us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 7.000s 282.325us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 178.000s 5611.178us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 4.000s 71.692us 1 1 100.00
csrng_err 1.000s 20.653us 1 1 100.00
csrng_sec_cm 3.000s 133.630us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 4.000s 71.692us 1 1 100.00
csrng_err 1.000s 20.653us 1 1 100.00
csrng_sec_cm 3.000s 133.630us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 4.000s 71.692us 1 1 100.00
csrng_err 1.000s 20.653us 1 1 100.00
csrng_sec_cm 3.000s 133.630us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 4.000s 71.692us 1 1 100.00
csrng_err 1.000s 20.653us 1 1 100.00
csrng_sec_cm 3.000s 133.630us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 4.000s 71.692us 1 1 100.00
csrng_err 1.000s 20.653us 1 1 100.00
csrng_sec_cm 3.000s 133.630us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 7.000s 282.325us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 4.000s 71.692us 1 1 100.00
csrng_err 1.000s 20.653us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 178.000s 5611.178us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 7.000s 282.325us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 6.000s 231.482us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 4.000s 71.692us 1 1 100.00
csrng_err 1.000s 20.653us 1 1 100.00
csrng_sec_cm 3.000s 133.630us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 4.000s 71.692us 1 1 100.00
csrng_err 1.000s 20.653us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 4.000s 71.692us 1 1 100.00
csrng_err 1.000s 20.653us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 4.000s 71.692us 1 1 100.00
csrng_err 1.000s 20.653us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 4.000s 71.692us 1 1 100.00
csrng_err 1.000s 20.653us 1 1 100.00
csrng_sec_cm 3.000s 133.630us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 4.000s 71.692us 1 1 100.00
csrng_err 1.000s 20.653us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 10802.126s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:671) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*]) 1 test run
csrng_cmds 27493375337907360620731026777467007207993561973082536143988140429604715922938 100
UVM_INFO @ 8101408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
csrng_stress_all_with_rand_reset 33808699341299739566830013030843556921090023449763185950319131957989160090667 None