Simulation Results: dma

 
25/05/2026 19:40:27 DVSim: v1.49.1 sha: f988e3e json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.09 %
  • code
  • 91.82 %
  • assert
  • 96.50 %
  • func
  • 60.95 %
  • block
  • 97.34 %
  • line
  • 96.85 %
  • branch
  • 95.76 %
  • toggle
  • 83.12 %
  • FSM
  • 91.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 5.000s 335.600us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 4.000s 956.048us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 5.000s 310.123us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 1.000s 57.707us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 1.000s 26.712us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 8.000s 592.693us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 3.000s 85.330us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 2.000s 28.451us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 1.000s 26.712us 1 1 100.00
dma_csr_aliasing 3.000s 85.330us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 21.000s 1489.807us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 180.000s 52421.177us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 44.000s 4179.381us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 44.000s 4179.381us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 180.000s 52421.177us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 134.000s 13223.856us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 44.000s 4179.381us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 9.000s 2353.020us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 214.000s 45141.261us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 1.000s 151.743us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 1.000s 48.903us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 3.000s 27.050us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 3.000s 27.050us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 1.000s 57.707us 1 1 100.00
dma_csr_rw 1.000s 26.712us 1 1 100.00
dma_csr_aliasing 3.000s 85.330us 1 1 100.00
dma_same_csr_outstanding 3.000s 496.753us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 1.000s 57.707us 1 1 100.00
dma_csr_rw 1.000s 26.712us 1 1 100.00
dma_csr_aliasing 3.000s 85.330us 1 1 100.00
dma_same_csr_outstanding 3.000s 496.753us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 21.000s 93.027us 1 1 100.00
dma_generic_stress 134.000s 13223.856us 1 1 100.00
dma_handshake_stress 44.000s 4179.381us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 5.000s 697.228us 1 1 100.00
tl_intg_err 2 2 100.00
dma_tl_intg_err 4.000s 1488.592us 1 1 100.00
dma_sec_cm 1.000s 35.529us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 101.000s 22557.886us 1 1 100.00
dma_longer_transfer 4.000s 579.536us 1 1 100.00
dma_stress_all_with_rand_reset 3.000s 104.708us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1287) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
dma_stress_all_with_rand_reset 73296371642569076645615814173614548017854040586208558010743634278422566292547 93
UVM_INFO @ 104707983ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---