Simulation Results: edn/edn0

 
25/05/2026 19:40:27 DVSim: v1.49.1 sha: f988e3e json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 76.96 %
  • code
  • 85.13 %
  • assert
  • 96.24 %
  • func
  • 49.51 %
  • block
  • 94.21 %
  • line
  • 97.07 %
  • branch
  • 87.52 %
  • toggle
  • 73.76 %
  • FSM
  • 82.17 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 2.000s 69.755us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 2.000s 67.619us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 2.000s 57.802us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 6.000s 509.942us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 2.000s 49.022us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 2.000s 112.711us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 2.000s 57.802us 1 1 100.00
edn_csr_aliasing 2.000s 49.022us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 3.000s 120.298us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 3.000s 120.298us 1 1 100.00
genbits 1 1 100.00
edn_genbits 3.000s 120.298us 1 1 100.00
interrupts 1 1 100.00
edn_intr 2.000s 23.559us 1 1 100.00
alerts 1 1 100.00
edn_alert 2.000s 33.077us 1 1 100.00
errs 1 1 100.00
edn_err 2.000s 21.871us 1 1 100.00
disable 2 2 100.00
edn_disable 1.000s 18.602us 1 1 100.00
edn_disable_auto_req_mode 2.000s 103.191us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 4.000s 916.129us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 2.000s 12.416us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.000s 23.157us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 3.000s 112.513us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 3.000s 112.513us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 2.000s 67.619us 1 1 100.00
edn_csr_rw 2.000s 57.802us 1 1 100.00
edn_csr_aliasing 2.000s 49.022us 1 1 100.00
edn_same_csr_outstanding 2.000s 20.690us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 2.000s 67.619us 1 1 100.00
edn_csr_rw 2.000s 57.802us 1 1 100.00
edn_csr_aliasing 2.000s 49.022us 1 1 100.00
edn_same_csr_outstanding 2.000s 20.690us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 5.000s 305.441us 1 1 100.00
edn_tl_intg_err 3.000s 145.030us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 2.000s 27.588us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 2.000s 33.077us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 5.000s 305.441us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 5.000s 305.441us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 5.000s 305.441us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 5.000s 305.441us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 2.000s 33.077us 1 1 100.00
edn_sec_cm 5.000s 305.441us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 2.000s 33.077us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 3.000s 145.030us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 22.000s 1320.825us 1 1 100.00