Simulation Results: edn/edn1

 
25/05/2026 19:40:27 DVSim: v1.49.1 sha: f988e3e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.53 %
  • code
  • 82.17 %
  • assert
  • 98.44 %
  • func
  • 78.99 %
  • line
  • 98.03 %
  • branch
  • 93.29 %
  • cond
  • 88.46 %
  • toggle
  • 85.62 %
  • FSM
  • 45.45 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.930s 55.441us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.210s 15.492us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.950s 25.128us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.100s 54.803us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.180s 36.170us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.140s 98.198us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.950s 25.128us 1 1 100.00
edn_csr_aliasing 1.180s 36.170us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 0.970s 236.386us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 0.970s 236.386us 1 1 100.00
genbits 1 1 100.00
edn_genbits 0.970s 236.386us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.000s 41.317us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.500s 168.403us 1 1 100.00
errs 1 1 100.00
edn_err 1.120s 21.196us 1 1 100.00
disable 2 2 100.00
edn_disable 0.980s 13.307us 1 1 100.00
edn_disable_auto_req_mode 1.320s 86.587us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.380s 76.234us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.910s 37.011us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.960s 28.661us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.610s 55.769us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.610s 55.769us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.210s 15.492us 1 1 100.00
edn_csr_rw 0.950s 25.128us 1 1 100.00
edn_csr_aliasing 1.180s 36.170us 1 1 100.00
edn_same_csr_outstanding 0.970s 109.923us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.210s 15.492us 1 1 100.00
edn_csr_rw 0.950s 25.128us 1 1 100.00
edn_csr_aliasing 1.180s 36.170us 1 1 100.00
edn_same_csr_outstanding 0.970s 109.923us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 2.510s 707.498us 1 1 100.00
edn_tl_intg_err 2.270s 358.679us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.860s 41.094us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.500s 168.403us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.510s 707.498us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.510s 707.498us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 2.510s 707.498us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 2.510s 707.498us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.500s 168.403us 1 1 100.00
edn_sec_cm 2.510s 707.498us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.500s 168.403us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.270s 358.679us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 15.810s 1971.347us 1 1 100.00