Simulation Results: hmac

 
25/05/2026 19:40:27 DVSim: v1.49.1 sha: f988e3e json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 74.23 %
  • code
  • 96.03 %
  • assert
  • 97.17 %
  • func
  • 29.49 %
  • block
  • 97.60 %
  • line
  • 98.35 %
  • branch
  • 93.99 %
  • toggle
  • 96.96 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 4.000s 137.595us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 1.000s 19.800us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 2.000s 50.904us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 6.000s 113.116us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 6.000s 374.599us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 2.000s 276.568us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 2.000s 50.904us 1 1 100.00
hmac_csr_aliasing 6.000s 374.599us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 74.000s 6763.911us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 15.000s 323.492us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 200.000s 41451.141us 1 1 100.00
hmac_test_sha384_vectors 389.000s 23061.057us 1 1 100.00
hmac_test_sha512_vectors 25.000s 277.710us 1 1 100.00
hmac_test_hmac256_vectors 18.000s 764.838us 1 1 100.00
hmac_test_hmac384_vectors 12.000s 389.062us 1 1 100.00
hmac_test_hmac512_vectors 17.000s 1611.908us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 14.000s 6880.579us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 66.000s 3947.124us 1 1 100.00
error 1 1 100.00
hmac_error 16.000s 1570.599us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 106.000s 44089.371us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 4.000s 137.595us 1 1 100.00
hmac_long_msg 74.000s 6763.911us 1 1 100.00
hmac_back_pressure 15.000s 323.492us 1 1 100.00
hmac_datapath_stress 66.000s 3947.124us 1 1 100.00
hmac_burst_wr 14.000s 6880.579us 1 1 100.00
hmac_stress_all 226.000s 11007.024us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 4.000s 137.595us 1 1 100.00
hmac_long_msg 74.000s 6763.911us 1 1 100.00
hmac_back_pressure 15.000s 323.492us 1 1 100.00
hmac_datapath_stress 66.000s 3947.124us 1 1 100.00
hmac_wipe_secret 106.000s 44089.371us 1 1 100.00
hmac_test_sha256_vectors 200.000s 41451.141us 1 1 100.00
hmac_test_sha384_vectors 389.000s 23061.057us 1 1 100.00
hmac_test_sha512_vectors 25.000s 277.710us 1 1 100.00
hmac_test_hmac256_vectors 18.000s 764.838us 1 1 100.00
hmac_test_hmac384_vectors 12.000s 389.062us 1 1 100.00
hmac_test_hmac512_vectors 17.000s 1611.908us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 4.000s 137.595us 1 1 100.00
hmac_long_msg 74.000s 6763.911us 1 1 100.00
hmac_back_pressure 15.000s 323.492us 1 1 100.00
hmac_datapath_stress 66.000s 3947.124us 1 1 100.00
hmac_burst_wr 14.000s 6880.579us 1 1 100.00
hmac_error 16.000s 1570.599us 1 1 100.00
hmac_wipe_secret 106.000s 44089.371us 1 1 100.00
hmac_test_sha256_vectors 200.000s 41451.141us 1 1 100.00
hmac_test_sha384_vectors 389.000s 23061.057us 1 1 100.00
hmac_test_sha512_vectors 25.000s 277.710us 1 1 100.00
hmac_test_hmac256_vectors 18.000s 764.838us 1 1 100.00
hmac_test_hmac384_vectors 12.000s 389.062us 1 1 100.00
hmac_test_hmac512_vectors 17.000s 1611.908us 1 1 100.00
hmac_stress_all 226.000s 11007.024us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 226.000s 11007.024us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 2.000s 11.779us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 1.000s 12.975us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 3.000s 458.989us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 3.000s 458.989us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 1.000s 19.800us 1 1 100.00
hmac_csr_rw 2.000s 50.904us 1 1 100.00
hmac_csr_aliasing 6.000s 374.599us 1 1 100.00
hmac_same_csr_outstanding 2.000s 361.888us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 1.000s 19.800us 1 1 100.00
hmac_csr_rw 2.000s 50.904us 1 1 100.00
hmac_csr_aliasing 6.000s 374.599us 1 1 100.00
hmac_same_csr_outstanding 2.000s 361.888us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.000s 166.853us 1 1 100.00
hmac_tl_intg_err 3.000s 89.371us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 3.000s 89.371us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 4.000s 137.595us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 3.000s 159.583us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 39.000s 2584.766us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 3.000s 114.086us 1 1 100.00