Simulation Results

Simulation Results: i2c

25/05/2026 19:40:27 DVSim: v1.49.1 sha: f988e3e json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
89.32 %

code
90.08 %

assert
96.83 %

func
81.05 %

block
96.28 %

line
95.71 %

branch
93.35 %

toggle
87.10 %

FSM
84.17 %

Validation stages

V1		100.00%
V2		80.49%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	48.000s	1394.228us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	20.000s	772.938us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	2.000s	19.026us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	1.000s	18.634us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	3.000s	118.938us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	2.000s	404.395us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	1.000s	86.651us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	1.000s	18.634us	1	1	100.00
	i2c_csr_aliasing	2.000s	404.395us	1	1	100.00

33/41 passed

80.49 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				1	1	100.00
	i2c_host_error_intr	2.000s	90.614us	1	1	100.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	2.000s	111.577us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	64.000s	7161.623us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	2.000s	48.252us	1	1	100.00
host_fifo_watermark				0	1	0.00
	i2c_host_fifo_watermark	3602.155s	0.000us	0	1	0.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	591.000s	4766.734us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	2.000s	190.217us	1	1	100.00
	i2c_host_fifo_fmt_empty	23.000s	373.916us	1	1	100.00
	i2c_host_fifo_reset_rx	8.000s	163.069us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	366.000s	2035.497us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	32.000s	1862.106us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	2.000s	691.941us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	3.000s	362.984us	0	1	0.00
target_stress_all				0	1	0.00
	i2c_target_stress_all	3600.000s	0.000us	0	1	0.00
target_maxperf				1	1	100.00
	i2c_target_perf	7.000s	2994.883us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	12.000s	936.270us	1	1	100.00
	i2c_target_intr_smoke	5.000s	835.348us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	3.000s	270.607us	1	1	100.00
	i2c_target_fifo_reset_tx	2.000s	242.282us	1	1	100.00
target_fifo_full				2	3	66.67
	i2c_target_stress_wr	3601.000s	0.000us	0	1	0.00
	i2c_target_stress_rd	12.000s	936.270us	1	1	100.00
	i2c_target_intr_stress_wr	1548.000s	11240.711us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	7.000s	1211.046us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	3.000s	1127.331us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	5.000s	729.702us	1	1	100.00
target_mode_glitch				0	1	0.00
	i2c_target_hrst	38.000s	10131.150us	0	1	0.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	5.000s	1788.998us	1	1	100.00
	i2c_target_fifo_watermarks_tx	2.000s	569.696us	1	1	100.00
host_mode_config_perf				1	2	50.00
	i2c_host_perf	64.000s	7161.623us	1	1	100.00
	i2c_host_perf_precise	3601.000s	0.000us	0	1	0.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	32.000s	1862.106us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	4.000s	228.551us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	5.000s	594.963us	1	1	100.00
	i2c_target_nack_acqfull_addr	3.000s	477.287us	1	1	100.00
	i2c_target_nack_txstretch	4.000s	239.034us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	18.000s	678.472us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	5.000s	2031.281us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	1.000s	33.764us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	1.000s	17.973us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	3.000s	103.059us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	3.000s	103.059us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	2.000s	19.026us	1	1	100.00
	i2c_csr_rw	1.000s	18.634us	1	1	100.00
	i2c_csr_aliasing	2.000s	404.395us	1	1	100.00
	i2c_same_csr_outstanding	2.000s	26.953us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	2.000s	19.026us	1	1	100.00
	i2c_csr_rw	1.000s	18.634us	1	1	100.00
	i2c_csr_aliasing	2.000s	404.395us	1	1	100.00
	i2c_same_csr_outstanding	2.000s	26.953us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	3.000s	564.581us	1	1	100.00
	i2c_sec_cm	1.000s	118.284us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	3.000s	564.581us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	3.000s	341.341us	1
target_error_intr				1
	i2c_target_unexp_stop	2.000s	220.625us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	3.000s	213.234us	1

Error Messages

	Test	seed	line	log context
Job timed out after * minutes				4 test runs
	i2c_host_fifo_watermark	17392959891620788063130679734552456014836099045623239119211128795760023954356	None
	i2c_host_perf_precise	108716389964653332539358280632124265650405220739605421698413961504350712099519	None
	i2c_target_stress_wr	92475704698230816081124504213974079291357597088416858354929417268197804119518	None
	i2c_target_stress_all	15571776680399440296571562415009190344145466655519357893718065606257593107880	None
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				2 test runs
	i2c_host_stress_all	113559619000665308998206546257123979924213845253761895829493004397693284957233	95	UVM_INFO @ 111576598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	37686680251237005572984183930551784529618030983936305501824634979683326741225	96	UVM_INFO @ 213234371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	95936269751286013818714305383800174896837274427955691284452219633221209084970	93	UVM_INFO @ 362984353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])				1 test run
	i2c_target_unexp_stop	86487174323412925884340380836349880808156881496484212547585979265775744274689	87	UVM_INFO @ 220625446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!				1 test run
	i2c_target_hrst	18307386880944499441744811061227604393283298117325879467634246673206636823914	88	UVM_INFO @ 10131150315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1287) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				1 test run
	i2c_host_stress_all_with_rand_reset	2831481566641654454716164859129625055802725619662513597804502470407224847941	93	UVM_INFO @ 341340628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared:				1 test run
	i2c_host_mode_toggle	24103014701669194070033685709698105011034659731323656126973136605220177334377	94	---------------------------------------------------- Name Type Size Value ---------------------------------------------------- mon_dut_item i2c_item - @17413