Simulation Results

Simulation Results: keymgr_dpe

25/05/2026 19:40:27 DVSim: v1.49.1 sha: f988e3e json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
66.25 %

code
84.04 %

assert
97.14 %

func
17.57 %

block
98.03 %

line
98.72 %

branch
93.41 %

toggle
62.50 %

FSM
81.54 %

Validation stages

V1		100.00%
V2		100.00%
V2S		100.00%

V1

6/6 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	keymgr_dpe_smoke	52.000s	33165.301us	1	1	100.00
csr_hw_reset				1	1	100.00
	keymgr_dpe_csr_hw_reset	2.000s	19.729us	1	1	100.00
csr_rw				1	1	100.00
	keymgr_dpe_csr_rw	2.000s	13.782us	1	1	100.00
csr_bit_bash				1	1	100.00
	keymgr_dpe_csr_bit_bash	7.000s	2796.036us	1	1	100.00
csr_aliasing				1	1	100.00
	keymgr_dpe_csr_aliasing	4.000s	603.959us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	keymgr_dpe_csr_mem_rw_with_rand_reset	2.000s	47.608us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	keymgr_dpe_csr_rw	2.000s	13.782us	1	1	100.00
	keymgr_dpe_csr_aliasing	4.000s	603.959us	1	1	100.00

V2

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
intr_test				1	1	100.00
	keymgr_dpe_intr_test	2.000s	10.598us	1	1	100.00
alert_test				1	1	100.00
	keymgr_dpe_alert_test	2.000s	21.096us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	keymgr_dpe_tl_errors	3.000s	65.464us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	keymgr_dpe_tl_errors	3.000s	65.464us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	keymgr_dpe_csr_hw_reset	2.000s	19.729us	1	1	100.00
	keymgr_dpe_csr_rw	2.000s	13.782us	1	1	100.00
	keymgr_dpe_csr_aliasing	4.000s	603.959us	1	1	100.00
	keymgr_dpe_same_csr_outstanding	3.000s	442.227us	1	1	100.00
tl_d_partial_access				4	4	100.00
	keymgr_dpe_csr_hw_reset	2.000s	19.729us	1	1	100.00
	keymgr_dpe_csr_rw	2.000s	13.782us	1	1	100.00
	keymgr_dpe_csr_aliasing	4.000s	603.959us	1	1	100.00
	keymgr_dpe_same_csr_outstanding	3.000s	442.227us	1	1	100.00

V2S

4/4 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	keymgr_dpe_sec_cm	10.000s	504.083us	1	1	100.00
	keymgr_dpe_tl_intg_err	5.000s	217.926us	1	1	100.00
shadow_reg_update_error				1	1	100.00
	keymgr_dpe_shadow_reg_errors	2.000s	113.984us	1	1	100.00
shadow_reg_read_clear_staged_value				1	1	100.00
	keymgr_dpe_shadow_reg_errors	2.000s	113.984us	1	1	100.00
shadow_reg_storage_error				1	1	100.00
	keymgr_dpe_shadow_reg_errors	2.000s	113.984us	1	1	100.00
shadowed_reset_glitch				1	1	100.00
	keymgr_dpe_shadow_reg_errors	2.000s	113.984us	1	1	100.00
shadow_reg_update_error_with_csr_rw				1	1	100.00
	keymgr_dpe_shadow_reg_errors_with_csr_rw	3.000s	197.676us	1	1	100.00
prim_count_check				1	1	100.00
	keymgr_dpe_sec_cm	10.000s	504.083us	1	1	100.00
prim_fsm_check				1	1	100.00
	keymgr_dpe_sec_cm	10.000s	504.083us	1	1	100.00