Simulation Results: kmac/masked

 
25/05/2026 19:40:27 DVSim: v1.49.1 sha: f988e3e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.69 %
  • code
  • 90.23 %
  • assert
  • 98.85 %
  • func
  • 94.99 %
  • line
  • 98.85 %
  • branch
  • 96.26 %
  • cond
  • 90.32 %
  • toggle
  • 99.51 %
  • FSM
  • 66.20 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 64.980s 4643.501us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 1.090s 61.870us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 1.010s 87.842us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 16.370s 3177.514us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 7.430s 1707.812us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 2.090s 318.358us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 1.010s 87.842us 1 1 100.00
kmac_csr_aliasing 7.430s 1707.812us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.950s 13.108us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.290s 26.482us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 152.190s 7600.603us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 38.090s 2451.073us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 1502.650s 70101.272us 1 1 100.00
kmac_test_vectors_sha3_256 31.500s 10957.122us 1 1 100.00
kmac_test_vectors_sha3_384 1455.200s 497787.000us 1 1 100.00
kmac_test_vectors_sha3_512 16.130s 2429.441us 1 1 100.00
kmac_test_vectors_shake_128 1739.430s 115688.081us 1 1 100.00
kmac_test_vectors_shake_256 347.610s 115447.405us 1 1 100.00
kmac_test_vectors_kmac 2.690s 310.220us 1 1 100.00
kmac_test_vectors_kmac_xof 2.830s 54.473us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 127.880s 5078.311us 1 1 100.00
app 1 1 100.00
kmac_app 108.160s 59554.147us 1 1 100.00
app_with_partial_data 1 1 100.00
kmac_app_with_partial_data 285.110s 9867.734us 1 1 100.00
entropy_refresh 1 1 100.00
kmac_entropy_refresh 230.820s 11028.376us 1 1 100.00
error 1 1 100.00
kmac_error 341.050s 65081.843us 1 1 100.00
key_error 1 1 100.00
kmac_key_error 5.450s 4228.790us 1 1 100.00
sideload_invalid 1 1 100.00
kmac_sideload_invalid 6.240s 253.969us 1 1 100.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 1.130s 26.081us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 0.920s 16.086us 1 1 100.00
entropy_ready_error 1 1 100.00
kmac_entropy_ready_error 25.530s 3514.459us 1 1 100.00
lc_escalation 1 1 100.00
kmac_lc_escalation 1.540s 67.942us 1 1 100.00
stress_all 1 1 100.00
kmac_stress_all 2212.690s 188025.036us 1 1 100.00
intr_test 1 1 100.00
kmac_intr_test 0.880s 43.046us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 1.200s 15.645us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 3.390s 94.505us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 3.390s 94.505us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 1.090s 61.870us 1 1 100.00
kmac_csr_rw 1.010s 87.842us 1 1 100.00
kmac_csr_aliasing 7.430s 1707.812us 1 1 100.00
kmac_same_csr_outstanding 1.880s 336.704us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 1.090s 61.870us 1 1 100.00
kmac_csr_rw 1.010s 87.842us 1 1 100.00
kmac_csr_aliasing 7.430s 1707.812us 1 1 100.00
kmac_same_csr_outstanding 1.880s 336.704us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 1.700s 39.578us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 1.700s 39.578us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 1.700s 39.578us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 1.700s 39.578us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 3.620s 116.680us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_sec_cm 63.710s 6296.972us 1 1 100.00
kmac_tl_intg_err 4.490s 1419.883us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 4.490s 1419.883us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 1.540s 67.942us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 64.980s 4643.501us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 127.880s 5078.311us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 1.700s 39.578us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 63.710s 6296.972us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 63.710s 6296.972us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 63.710s 6296.972us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 64.980s 4643.501us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 1.540s 67.942us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 63.710s 6296.972us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 1 1 100.00
kmac_mubi 121.060s 6718.392us 1 1 100.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 64.980s 4643.501us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
kmac_stress_all_with_rand_reset 124.580s 2509.739us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:858) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) 1 test run
kmac_stress_all_with_rand_reset 38606643377045544438340450154852006630850141131473666318958900172747589768115 389
UVM_INFO @ 2509738989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---