Simulation Results: kmac/unmasked

 
25/05/2026 19:40:27 DVSim: v1.49.1 sha: f988e3e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.48 %
  • code
  • 89.16 %
  • assert
  • 98.50 %
  • func
  • 92.78 %
  • line
  • 97.28 %
  • branch
  • 95.31 %
  • cond
  • 93.77 %
  • toggle
  • 99.92 %
  • FSM
  • 59.50 %
Validation stages
V1
100.00%
V2
96.55%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 37.930s 9143.358us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 1.210s 83.858us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 1.200s 42.817us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 9.380s 2862.836us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 3.730s 224.637us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 2.140s 82.733us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 1.200s 42.817us 1 1 100.00
kmac_csr_aliasing 3.730s 224.637us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.910s 36.293us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.590s 40.079us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 1221.490s 16225.307us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 34.490s 2446.954us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 1188.420s 17662.617us 1 1 100.00
kmac_test_vectors_sha3_256 33.210s 16541.628us 1 1 100.00
kmac_test_vectors_sha3_384 17.370s 833.177us 1 1 100.00
kmac_test_vectors_sha3_512 13.980s 4117.865us 1 1 100.00
kmac_test_vectors_shake_128 2425.680s 383154.990us 1 1 100.00
kmac_test_vectors_shake_256 105.820s 8266.263us 1 1 100.00
kmac_test_vectors_kmac 1.680s 154.704us 1 1 100.00
kmac_test_vectors_kmac_xof 1.750s 102.533us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 244.870s 4524.589us 1 1 100.00
app 1 1 100.00
kmac_app 60.070s 8538.630us 1 1 100.00
app_with_partial_data 1 1 100.00
kmac_app_with_partial_data 77.360s 6092.832us 1 1 100.00
entropy_refresh 1 1 100.00
kmac_entropy_refresh 35.790s 3282.690us 1 1 100.00
error 1 1 100.00
kmac_error 146.600s 40995.003us 1 1 100.00
key_error 1 1 100.00
kmac_key_error 9.820s 3249.046us 1 1 100.00
sideload_invalid 0 1 0.00
kmac_sideload_invalid 44.060s 10044.561us 0 1 0.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 22.850s 6386.200us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 29.620s 3681.913us 1 1 100.00
entropy_ready_error 1 1 100.00
kmac_entropy_ready_error 42.620s 14928.322us 1 1 100.00
lc_escalation 1 1 100.00
kmac_lc_escalation 1.720s 63.257us 1 1 100.00
stress_all 1 1 100.00
kmac_stress_all 1472.800s 509547.734us 1 1 100.00
intr_test 1 1 100.00
kmac_intr_test 0.940s 14.514us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 1.180s 20.444us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 1.760s 71.537us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 1.760s 71.537us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 1.210s 83.858us 1 1 100.00
kmac_csr_rw 1.200s 42.817us 1 1 100.00
kmac_csr_aliasing 3.730s 224.637us 1 1 100.00
kmac_same_csr_outstanding 2.500s 248.576us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 1.210s 83.858us 1 1 100.00
kmac_csr_rw 1.200s 42.817us 1 1 100.00
kmac_csr_aliasing 3.730s 224.637us 1 1 100.00
kmac_same_csr_outstanding 2.500s 248.576us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 1.440s 122.576us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 1.440s 122.576us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 1.440s 122.576us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 1.440s 122.576us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 4.970s 252.738us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_sec_cm 18.900s 1604.507us 1 1 100.00
kmac_tl_intg_err 2.520s 216.539us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 2.520s 216.539us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 1.720s 63.257us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 37.930s 9143.358us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 244.870s 4524.589us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 1.440s 122.576us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 18.900s 1604.507us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 18.900s 1604.507us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 18.900s 1604.507us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 37.930s 9143.358us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 1.720s 63.257us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 18.900s 1604.507us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 1 1 100.00
kmac_mubi 136.860s 2895.911us 1 1 100.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 37.930s 9143.358us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
kmac_stress_all_with_rand_reset 76.960s 2096.656us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4) 1 test run
kmac_sideload_invalid 63332893852610716393193466780006600728082905512956127246248906223700466060442 81
UVM_INFO @ 10044560861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---