Simulation Results: lc_ctrl/volatile_unlock_disabled

 
25/05/2026 19:40:27 DVSim: v1.49.1 sha: f988e3e json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.06 %
  • code
  • 93.19 %
  • assert
  • 96.69 %
  • func
  • 86.31 %
  • block
  • 96.61 %
  • line
  • 97.26 %
  • branch
  • 91.38 %
  • toggle
  • 88.87 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 30.924us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 25.878us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.000s 56.864us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 3.000s 95.164us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 75.656us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 60.787us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.000s 56.864us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 75.656us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.000s 102.009us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 6.000s 966.365us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.000s 41.697us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 3.000s 46.592us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 3.000s 728.446us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 7.000s 3479.572us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 3.000s 728.446us 1 1 100.00
lc_ctrl_prog_failure 3.000s 46.592us 1 1 100.00
lc_ctrl_errors 7.000s 3479.572us 1 1 100.00
lc_ctrl_security_escalation 4.000s 606.326us 1 1 100.00
lc_ctrl_jtag_state_failure 14.000s 1503.132us 1 1 100.00
lc_ctrl_jtag_prog_failure 7.000s 384.290us 1 1 100.00
lc_ctrl_jtag_errors 11.000s 5183.546us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 4.000s 602.606us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.000s 490.893us 1 1 100.00
lc_ctrl_jtag_prog_failure 7.000s 384.290us 1 1 100.00
lc_ctrl_jtag_errors 11.000s 5183.546us 1 1 100.00
lc_ctrl_jtag_access 7.000s 496.105us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 8.000s 967.727us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.000s 90.354us 1 1 100.00
lc_ctrl_jtag_csr_rw 4.000s 555.713us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 9.000s 613.945us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 6.000s 965.958us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 67.890us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.000s 210.346us 1 1 100.00
lc_ctrl_jtag_alert_test 3.000s 397.923us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 2.000s 339.094us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.000s 21.610us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 105.000s 6470.379us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 105.426us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 46.910us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 46.910us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 25.878us 1 1 100.00
lc_ctrl_csr_rw 1.000s 56.864us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 75.656us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.000s 50.349us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 25.878us 1 1 100.00
lc_ctrl_csr_rw 1.000s 56.864us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 75.656us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.000s 50.349us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 4.000s 1003.503us 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 721.428us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 721.428us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 6.000s 966.365us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 3.000s 728.446us 1 1 100.00
lc_ctrl_sec_cm 4.000s 1003.503us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 3.000s 728.446us 1 1 100.00
lc_ctrl_sec_cm 4.000s 1003.503us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 3.000s 728.446us 1 1 100.00
lc_ctrl_sec_cm 4.000s 1003.503us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 3.000s 728.446us 1 1 100.00
lc_ctrl_sec_cm 4.000s 1003.503us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 3.000s 728.446us 1 1 100.00
lc_ctrl_sec_cm 4.000s 1003.503us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 3.000s 728.446us 1 1 100.00
lc_ctrl_sec_cm 4.000s 1003.503us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 3.000s 728.446us 1 1 100.00
lc_ctrl_sec_cm 4.000s 1003.503us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 3.000s 728.446us 1 1 100.00
lc_ctrl_sec_cm 4.000s 1003.503us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.000s 606.326us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 4.000s 102.009us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.000s 490.893us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.000s 837.477us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.000s 837.477us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 7.000s 802.991us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.000s 1326.794us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.000s 1326.794us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 12.000s 2061.724us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 76974803304364486540340272389122187768775897429229736743760599921254531776273 358
UVM_INFO @ 2061723998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---