Simulation Results: lc_ctrl/volatile_unlock_enabled

 
25/05/2026 19:40:27 DVSim: v1.49.1 sha: f988e3e json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.21 %
  • code
  • 94.36 %
  • assert
  • 95.97 %
  • func
  • 86.31 %
  • block
  • 97.16 %
  • line
  • 97.69 %
  • branch
  • 92.79 %
  • toggle
  • 89.33 %
  • FSM
  • 97.62 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 3.000s 197.071us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.000s 16.722us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.000s 52.203us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.000s 72.044us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 70.953us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 94.414us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.000s 52.203us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 70.953us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.000s 222.192us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 13.000s 1231.694us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 2.000s 41.825us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 3.000s 242.970us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 7.000s 1609.596us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 4.000s 245.693us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 7.000s 1609.596us 1 1 100.00
lc_ctrl_prog_failure 3.000s 242.970us 1 1 100.00
lc_ctrl_errors 4.000s 245.693us 1 1 100.00
lc_ctrl_security_escalation 5.000s 1819.582us 1 1 100.00
lc_ctrl_jtag_state_failure 30.000s 1675.078us 1 1 100.00
lc_ctrl_jtag_prog_failure 5.000s 1367.757us 1 1 100.00
lc_ctrl_jtag_errors 12.000s 7461.344us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 4.000s 298.407us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.000s 672.250us 1 1 100.00
lc_ctrl_jtag_prog_failure 5.000s 1367.757us 1 1 100.00
lc_ctrl_jtag_errors 12.000s 7461.344us 1 1 100.00
lc_ctrl_jtag_access 5.000s 410.085us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 8.000s 4306.481us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.000s 51.450us 1 1 100.00
lc_ctrl_jtag_csr_rw 3.000s 42.122us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 7.000s 2389.721us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.000s 285.465us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 26.173us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.000s 472.078us 1 1 100.00
lc_ctrl_jtag_alert_test 1.000s 921.245us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 6.000s 1125.861us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 21.140us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 116.000s 7417.088us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 13.846us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 258.729us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 258.729us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 16.722us 1 1 100.00
lc_ctrl_csr_rw 1.000s 52.203us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 70.953us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 57.518us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 16.722us 1 1 100.00
lc_ctrl_csr_rw 1.000s 52.203us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 70.953us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 57.518us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 12.000s 7342.420us 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 106.412us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 106.412us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 13.000s 1231.694us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 7.000s 1609.596us 1 1 100.00
lc_ctrl_sec_cm 12.000s 7342.420us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 7.000s 1609.596us 1 1 100.00
lc_ctrl_sec_cm 12.000s 7342.420us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.000s 1609.596us 1 1 100.00
lc_ctrl_sec_cm 12.000s 7342.420us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.000s 1609.596us 1 1 100.00
lc_ctrl_sec_cm 12.000s 7342.420us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 7.000s 1609.596us 1 1 100.00
lc_ctrl_sec_cm 12.000s 7342.420us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.000s 1609.596us 1 1 100.00
lc_ctrl_sec_cm 12.000s 7342.420us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.000s 1609.596us 1 1 100.00
lc_ctrl_sec_cm 12.000s 7342.420us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 7.000s 1609.596us 1 1 100.00
lc_ctrl_sec_cm 12.000s 7342.420us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.000s 1819.582us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.000s 222.192us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.000s 672.250us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 8.000s 883.103us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 8.000s 883.103us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 6.000s 3340.002us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.000s 1301.758us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.000s 1301.758us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 18.000s 2126.349us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 4811630001454630208308566980673874416809919206140521760533547750205710404944 745
UVM_INFO @ 2126348802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---