Simulation Results: mbx

 
25/05/2026 19:40:27 DVSim: v1.49.1 sha: f988e3e json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 90.31 %
  • code
  • 90.31 %
  • assert
  • 97.15 %
  • func
  • 83.46 %
  • block
  • 95.74 %
  • line
  • 96.16 %
  • branch
  • 88.65 %
  • toggle
  • 86.12 %
Validation stages
V1
100.00%
V2
63.64%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_smoke 1 1 100.00
mbx_smoke 56.000s 6638.160us 1 1 100.00
csr_hw_reset 1 1 100.00
mbx_csr_hw_reset 1.000s 52.952us 1 1 100.00
csr_rw 1 1 100.00
mbx_csr_rw 1.000s 23.480us 1 1 100.00
csr_bit_bash 1 1 100.00
mbx_csr_bit_bash 4.000s 737.248us 1 1 100.00
csr_aliasing 1 1 100.00
mbx_csr_aliasing 2.000s 71.332us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
mbx_csr_mem_rw_with_rand_reset 1.000s 143.048us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
mbx_csr_rw 1.000s 23.480us 1 1 100.00
mbx_csr_aliasing 2.000s 71.332us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_stress 0 1 0.00
mbx_stress 5.000s 650.573us 0 1 0.00
mbx_max_activity 0 1 0.00
mbx_stress_zero_delays 5.000s 347.172us 0 1 0.00
mbx_imbx_oob 0 1 0.00
mbx_imbx_oob 9.000s 1658.863us 0 1 0.00
mbx_doe_intr_msg 1 1 100.00
mbx_doe_intr_msg 9.000s 2956.977us 1 1 100.00
alert_test 1 1 100.00
mbx_alert_test 1.000s 17.711us 1 1 100.00
intr_test 1 1 100.00
mbx_intr_test 2.000s 22.296us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
mbx_tl_errors 2.000s 7.137us 0 1 0.00
tl_d_illegal_access 0 1 0.00
mbx_tl_errors 2.000s 7.137us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
mbx_csr_hw_reset 1.000s 52.952us 1 1 100.00
mbx_csr_rw 1.000s 23.480us 1 1 100.00
mbx_csr_aliasing 2.000s 71.332us 1 1 100.00
mbx_same_csr_outstanding 1.000s 19.282us 1 1 100.00
tl_d_partial_access 4 4 100.00
mbx_csr_hw_reset 1.000s 52.952us 1 1 100.00
mbx_csr_rw 1.000s 23.480us 1 1 100.00
mbx_csr_aliasing 2.000s 71.332us 1 1 100.00
mbx_same_csr_outstanding 1.000s 19.282us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
mbx_tl_intg_err 2.000s 985.486us 1 1 100.00
mbx_sec_cm 1.000s 12.477us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (mbx_scoreboard.sv:500) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) RDATA read data mismatched 2 test runs
mbx_stress 73264508504771885831130820435095879273080240282027157554195801007852154907156 152
UVM_INFO @ 650573304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
mbx_stress_zero_delays 98362228855433742934381864952014796516811613259240039560721713012456789494223 378
UVM_INFO @ 347171501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register 1 test run
mbx_imbx_oob 75594530854067016226945721938425166417856161629876494419949019265256775381048 128
UVM_INFO @ 1658862912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:582) scoreboard [scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted *, but saw *). 1 test run
mbx_tl_errors 73248778182624663718892627689439128637317134954794230992291034575886192399795 85
TL item was: req: (cip_tl_seq_item@19553) { a_addr: 'h92857f54 a_data: 'h17483471 a_mask: 'h3 a_size: 'h2 a_param: 'h0 a_source: 'h61 a_opcode: 'h1 a_user: 'h2583f d_param: 'h0 d_source: 'h61 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 7136853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---